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105-586: The first line of computer systems given the DECstation name were word processing systems based on the PDP-8 . These systems, built into a VT52 terminal , were also known as the VT78 . The second (and completely unrelated) line of DECstations began with the DECstation 3100, which was released on 11 January 1989. The DECstation 3100 was the first commercially available RISC -based machine built by DEC. This line of DECstations

210-574: A light pen , analog-to-digital converters , digital-to-analog converters , tape drives , and disk drives . To save money, the design uses inexpensive main memory for many purposes that are served by more expensive flip-flop registers in other computers, such as auxiliary counters and subroutine linkage. Basic models use software to do multiplication and division. For faster math, the Extended Arithmetic Element (EAE) provides multiply and divide instructions with an additional register,

315-414: A program counter (PC), and a carry flag called the "link register" (L). Additional registers not visible to the programmer are a memory-buffer register and a memory-address register . To save money, these serve multiple purposes at different points in the operating cycle. For example, the memory buffer register provides arithmetic operands, is part of the instruction register, and stores data to rewrite

420-434: A 1 MB secondary cache. These systems have 8 MB of onboard memory and four SIMM slots that can be used to expand the amount of memory by 32 MB, for a total of 40 MB of memory. These SIMM slots accept 2 and 8 MB SIMMs in pairs. All SIMMs in the system must be of the same size. The memory bus is 40 bits wide, with 32 bits used for data and four bits used to for byte-parity. The Memory Control ASIC controls

525-461: A 16 × 16 pixel, 2-bit color cursor. The color frame buffer has an 8-bit write mask, also known as a "planemask", used to select which pixels are to be updated. None of the framebuffers use all the memory provided by the frame buffer module, this being organized as 1024 × 1024 pixels, and thus only the uppermost 864 pixels are used for the display. Unused areas of the frame buffer memory may be used to store graphical structures such as fonts, although this

630-592: A 2.0 version scheduled for the summer of that year. However, during a period of strategic uncertainty only weeks later in 1992, DEC appeared to abandon plans to officially provide OSF/1 on MIPS-based DECstations, instead re-emphasising ULTRIX for these models whilst intending to offer OSF/1 for the company's impending Alpha-based product lines. At this time, the DECstation 2100, 3100, 3100S, 5000–120, 5000–125 and 5000–200 models were stated as being able to run OSF/1, along with certain DECsystem models. User dissatisfaction with

735-402: A 24-bit buffer for storing off-screen pixmaps in addition to the 24-bit Z-buffer and double buffer. PDP-8 The PDP-8 is a family of 12-bit minicomputers that was produced by Digital Equipment Corporation (DEC) . It was the first commercially successful minicomputer, with over 50,000 units being sold over the model's lifetime. Its basic design follows the pioneering LINC but has

840-463: A 256-entry 24-bit color look up table, which selects 256 colors for display out of a palette of 16,777,216. The frame buffer is treated as part of the memory subsystem. The I/O subsystem provides the system with an 8-bit single-ended SCSI bus, 10 Mbit/s Ethernet, serial line, the Serial Desktop Bus and analog audio. SCSI is provided by a NCR 53C94 ASC (Advanced SCSI Controller). Ethernet

945-458: A 400 W power supply is located at the rear of the drawer. The H9A00 enclosure, a 19-inch rack , contains a minimum of one CPU drawer and one mass storage drawer. A power controller at the bottom of the enclosure distributed power to the CPU and mass storage drawers. The rack can contain a maximum of two CPU drawers and four mass storage drawers. The DECsystem 5900 has a width of 61 cm (24 in),

1050-493: A 64 KB direct-mapped write-through data cache with a cache line size of four bytes. Four R2020 implement a four-stage write buffer to improve performance by permitting the R2000 to write to its write-through data cache without stalling. The R2000 microprocessor could be configured to run either in big-endian or little-endian mode. In the DECstation family, the decision was made to run little-endian to maintain compatibility with both

1155-486: A 64 KB instruction cache and a 64 KB data cache. The Model 133 has a 128 KB instruction cache. These systems support 16 to 128 MB of memory through 16 SIMM slots that accept 2 or 8 MB SIMMs. Only one type of SIMM may be used, 2 and 8 MB SIMMs cannot be mixed in the same system. The 2 MB SIMM is identical to the SIMM used in the DECstation 2100 and 3100, allowing upgrades from these older systems to

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1260-425: A CPU module, a system module and a power supply located on left side of the enclosure. They do not have any internal storage capability. Drives were intended to be installed in external single- or multiple-drive enclosures. These enclosures were connected to system via a SCSI connector located at the rear of the system. Alternatively, storage was to be provided by a file server accessed over a network. Each member of

1365-490: A JMP. The OPR instruction was said to be "microcoded." This did not mean what the word means today (that a lower-level program fetched and interpreted the OPR instruction), but meant that each bit of the instruction word specifies a certain action, and the programmer could achieve several actions in a single instruction cycle by setting multiple bits. In use, a programmer can write several instruction mnemonics alongside one another, and

1470-555: A Kaypro 386 (an 80386-based computer) and was written in the C computer language (before the ANSI-C standard was finalized) and assembler by David Beecher of Denver, Colorado. It replaced a failing PDP-8/S computer that operated the fuel handling machine at Reactor #85, the Platteville, Colorado Nuclear Fuel powered Electric Generating Station, Ft. St. Vrain. It was reviewed by Rockwell International and performed flawlessly for 2.5 years during

1575-512: A Model 240 to a Model 260. Differences in the provision of the CPU subsystem had an impact on the design of CPU upgrades to the DECstation range. "Snap-in" upgrades providing the R4000 CPU, designed as replacement CPU modules, were announced for "all current DECstations" in 1992. However, a CPU upgrade for the Model 200 required a replacement motherboard. The Model 200 Series has 15 SIMM slots located on

1680-475: A PDP-8 are available on the Internet, as well as open-source hardware re-implementations. The best of these correctly execute DEC's operating systems and diagnostic software. The software simulations often simulate late-model PDP-8s with all possible peripherals. Even these use only a tiny fraction of the capacity of a modern personal computer. One of the first commercial versions of a PDP-8/S virtual machine ran on

1785-497: A bank of 12 toggle switches. Typically, these instructions were a bootstrap loader to read a program from the paper tape reader. Program development could then proceed, using paper tape input and output. Paper-tape versions of a number of programming languages became available, including DEC's FOCAL interpreter and a 4K FORTRAN compiler and runtime. Toward the end of the PDP-8 era, operating systems such as OS/8 and COS-310 allowed

1890-463: A chipset consisting of a 20, 25 or 33 MHz R3000A CPU and R3010 FPU accompanied by a 64 KB instruction cache and a 64 KB data cache. Both caches are direct-mapped and have a 4-byte cache line. The data cache is write through. All components on the CPU module operate at the same clock frequency as the R300A. A CPUCTL ASIC is also present, its purpose to provide interfacing and buffering between

1995-608: A daughter card, the CPU module, and does not use a processor chipset, featuring a single 40 MHz R3400 instead. The R3400 integrates the R3000A CPU and the R3010 FPU in a single die and package. The processor's external 64 KB instruction cache and 64 KB data cache is connected to the R3400 by a 40 MHz bus that also serves as the datapath to the MB ASIC. The Model 260's CPU subsystem

2100-474: A further three discrete components used in the Model 200. The Model 200 Series uses the TURBOchannel Interconnect for expansion and all models have three TURBOchannel option slots. The Model 200 provides 4 MB of physical address space for each TURBOchannel option, while the Model 240 and 260 provides 8 MB. TURBOchannel in the Model 240 and 260 is clocked at 25 MHz. In the Model 240 and 260,

2205-535: A large cabinet. In the later 8/S model, introduced in August 1966, two different logic voltages increased the fan-out of the inexpensive diode–transistor logic . The 8/S also reduced the number of logic gates by using a serial, single-bit-wide data path to do arithmetic. The CPU of the PDP-8/S has only about 519 logic gates . In comparison, small microcontrollers (as of 2008) usually have 15,000 or more. The reductions in

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2310-421: A machine about the size of a small household refrigerator . It was the first computer to be sold for under $ 20,000, making it the best-selling computer in history at that time. The Straight-8 was supplanted in 1966 by the PDP-8/S, which was available in desktop and rack-mount models. Using a one-bit serial arithmetic logic unit (ALU) allowed the PDP-8/S to be smaller and less expensive, although slower than

2415-477: A memory word, except if indirection is specified, but has the same bit fields. This use of the instruction word divides the 4,096-word memory into 128-word pages ; bit 4 of the instruction selects either the current page or page 0 (addresses 0000–0177 in octal ). Memory in page 0 is at a premium, since variables placed here can be addressed directly from any page. (Moreover, address 0000 is where any interrupt service routine must start, and addresses 0010–0017 have

2520-424: A resolution of 1280 × 1024 and a refresh rate of either 66 or 72 Hz. The PXG also has an 8-bit or 24-bit Z-buffer and is double buffered . The color depth and the depth of Z-buffer can be extended by installing additional VSIMMs or Z-buffer modules on the module. The PXG Turbo variants are capable of 24-bit color, a resolution of 1280 × 1024 and a refresh rate of either 66 or 72 Hz. They differ by featuring

2625-489: A six-bit teleprinter code called the teletypesetting or TTS code was in widespread use by the news wire services, and an early application for the PDP-8 was typesetting using this code. PDP-8 instructions have a three-bit opcode, so there are only eight instructions. The programmer can use many additional instruction mnemonics, which the assembler translates to specific OPR or IOT instructions. The PDP-8 has only three programmer-visible registers : A 12-bit accumulator (AC),

2730-613: A smaller instruction set , which is an expanded version of the PDP-5 instruction set. Similar machines from DEC are the PDP-12 which is a modernized version of the PDP-8 and LINC concepts, and the PDP-14 industrial controller system. The earliest PDP-8 model, informally known as a "Straight-8", was introduced on 22 March 1965 priced at $ 18,500 (equivalent to about $ 178,900 in 2023 ). It uses diode–transistor logic packaged on flip chip cards in

2835-469: A speed of 0.333 MIPS . The 1974 Pocket Reference Card for the PDP-8/E gives a basic instruction time of 1.2 microseconds, or 2.6 microseconds for instructions that reference memory. The PDP-8 was designed in part to handle contemporary telecommunications and text. Six-bit character codes were in widespread use at the time, and the PDP-8's twelve-bit words can efficiently store two such characters. In addition,

2940-474: A subroutine produces defects that are difficult to trace to the subroutine in question. As design advances reduced the costs of logic and memory, the programmer's time became relatively more important. Subsequent computer designs emphasized ease of programming, typically using larger and more intuitive instruction sets. Eventually, most machine code was generated by compilers and report generators. The reduced instruction set computer returned full-circle to

3045-489: A traditional line mode editor and command-line compiler development system using languages such as PAL-III assembly language, FORTRAN, BASIC , and DIBOL . Fairly modern and advanced real-time operating system (RTOS) and preemptive multitasking multi-user systems were available: a real-time system (RTS-8) was available as were multiuser commercial systems (COS-300 and COS-310) and a dedicated single-user word-processing system (WPS-8). A time-sharing system, TSS-8 ,

3150-456: Is 32 bits wide to match the native word length of the R3000. The memory subsystem is protected by an ECC scheme with seven bits of check for every 32-bit transaction. The SIMMs are two-way interleaved using the low-order method, where even and odd memory addresses are treated as separate banks of memory. Interleaving the memory subsystem doubles the bandwidth of a non-interleaved memory subsystem using

3255-581: Is a Motorola MC146818, which also has 50 bytes of RAM for storing console configuration information, and the 256 KB of ROM for storing boot-strap and self-test software is provided by two 128 KB ROMs in DIP sockets. The enclosure used by the DECstation 3100 and 2100 is identical to the enclosure used by the VAXstation 3100 as these systems use a mechanically identical system module. The enclosure can accommodate two 3.5-inch drives, which are mounted on trays above

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3360-403: Is also 12 bits, so the PDP-8's basic configuration has a main memory of 4,096 (2 ) twelve-bit words, or 6  KiB in modern terms. An optional memory-expansion unit can switch banks of memories using an IOT instruction. The memory is magnetic-core memory with a cycle time of 1.5 microseconds (0.667 MHz ), so that a typical two-cycle (Fetch, Execute) memory-reference instruction runs at

3465-457: Is also featured, as is a 256 KB system boot-strap and diagnostic ROM in a socket. In contrast, the Model 240's and 260's I/O subsystem is based around an I/O Controller ASIC that serves as a bridge between TURBOchannel and the two I/O buses it implements. I/O devices such as the two Zilog Z85C30 SCCs (Serial Communications Controller), a NCR 53C94 ASC, an AMD 7990 LANCE, Dallas Semiconductor DS1287 real time clock and system ROM are connected to

3570-524: Is also located on a CPU module daughter card, but it features a 120 MHz (60 MHz external) R4000 with internal instruction and data caches and an external secondary cache. The Model 260's CPU subsystem is unique in the Model 200 Series as it contains the boot ROM firmware , unlike the other members, which have their boot ROM located in the system module. This difference is due to the R4000 requiring different firmware that could not be replaced when upgrading

3675-595: Is connected to the internal 3.5 drive bays and an external port (HONDA68 male connector) to be connected to drive expansion boxes. These systems have four asynchronous serial lines that are provided by a DC7085 gate array. Of the four serial lines, only the third line has the required modem control signals to support a modem. A 4-pin MMJ connector is provided for the keyboard line, a 7-pin DIN connector for mouse line, and two 6-pin MMJ connectors for printer and modem lines. The real time clock

3780-497: Is implemented by an AMD 7992 SIA ( Serial Interface Adapter ) and a BNC ThinWire connector. The 8-bit, single-ended SCSI bus is provided by an NCR 53C94 ASC (Advanced SCSI Controller). Both integrated option modules have 128 KB of SRAM each serving as a buffer to improve performance. Four serial lines are also provided for the keyboard, mouse, communications port and printer. These lines are implemented by two DC7085s. A Dallas Semiconductor DS1287 real time clock with 50 bytes of NVRAM

3885-564: Is provided by an AMD Am7990 LANCE (Local Area Network Controller for Ethernet) and an AMD Am7992 SIA (Serial Interface Adapter) that implements the AUI interface. A single serial port capable of 50 to 19,200 baud with full modem control capability is provided by a Zilog Z85C30 SCC (Serial Communications Controller). Analog audio and ISDN support is provided by an AMD 79C30A DSC (Digital Subscriber Controller). These devices are connected to IOCTL ASIC via two 8-bit buses or one 16-bit bus. The ASIC interfaces

3990-400: Is set. More complicated devices, such as disk drives, use these 3 bits in device-specific fashions. Typically, a device decodes the 3 bits to give 8 possible function codes. Many operations are achieved using OPR, including most of the conditionals. OPR does not address a memory location; conditional execution is achieved by conditionally skipping the following instruction, which is typically

4095-509: Is shipped in a BA430 enclosure, which provides a 12-slot backplane and room for four mass storage devices. The base system contains the following: The DECsystem 5800 Series are high-end multiprocessor systems. The series comprised the DECsystem 5810, 5820, 5830, and 5840, with the third digit referring to the number of processors. These systems can be considered to be the MIPS/RISC alternatives of

4200-454: Is the same in all groups is bit 4, CLA. If set, the accumulator is cleared. In most cases, the operations are sequenced so that they can be combined in the most useful ways. For example, combining CLA (CLear Accumulator), CLL (CLear Link), and IAC (Increment ACcumulator) first clears the AC and Link, then increments the accumulator, leaving it set to 1. Adding RAL to the mix (so CLA CLL IAC RAL) causes

4305-502: Is useful only when optional software is installed. The Model 200 uses discrete components to implement the memory subsystem logic. In the Model 240, these discrete components are replaced by three ASICs, the MB ASIC, the MT ASIC and the MS ASIC. The MB (Memory Buffer) ASIC serves as an interface between the 40 MHz CPU module domain and the 25 MHz system module domain. It is connected to

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4410-550: The DEC 3000 AXP series, were similar in some respects to contemporaneous MIPS-based DECstations, which were sold alongside the Alpha systems as the DECstation line was gradually phased out. Both used the TURBOchannel expansion bus for video and network cards, as well as being sold with the same TURBOchannel option modules, mice, monitors, and keyboards. Later DECstations planned to be based on

4515-508: The ECL -based R6000 were canceled on 14 August 1990 after Bipolar Integrated Technology failed to deliver sufficient volumes of the microprocessor, which was difficult to fabricate. Yields of the R6000 were further reduced as DEC required the little-endian mode used from the beginning to continue to be available. The MIPS-based DECstations were used as the first target system and development platform for

4620-733: The Mach microkernel , as well as early development of the Windows NT operating system. More recently, various free operating systems such as NetBSD and Linux /MIPS have been ported to the MIPS-based DECstations, extending their useful life by providing a modern operating system. DEC originally planned to introduce OSF/1 as its chosen Unix product, starting with a 1.0 version in March 1992 that promised to offer several enhancements over ULTRIX, albeit with some deficiencies that were meant to be fixed in

4725-563: The VAX family and the growing population of Intel-based PC's. The DECstation 3100 and 2100's memory system contains both the DRAM -based system memory and VRAM -based framebuffers. The amount of system memory supported is 4 to 24 MB, organized into six physical memory banks. These systems has 12 SIMM slots that use 2 MB SIMMs, with each SIMM containing 1,048,576 word × 18-bit DRAMs. The SIMMs are installed in pairs (in increments of 4 MB) and

4830-559: The VAX 6000 operating the XMI and BI bus. The 5810 and 5820, using 25 MHz R3000 microprocessors and R3010 floating-point coprocessors, were introduced on 11 July 1989. Code name ISIS. The DECsystem 5900 and DECsystem 5900/260 are rack-mounted DECstation 5000 Model 240 and DECstation Model 260 workstations, respectively, positioned as mid-range servers by Digital. The DECsystem 5900 was introduced in early December 1991. Both models were discontinued on 28 January 1994. Their intended replacement

4935-561: The VAXstation 3100 which was introduced at about the same time. Server configurations of DECstation models, distributed without a framebuffer or a graphics accelerator, both Turbochannel and Q-bus based, were called " DECsystem " but should not be confused with some PDP-10 machines of the same name. Early models of the DECstation were heavily integrated systems with little expansion capability and do not even possess expansion buses. The DECstation 5000 systems, introduced later, improved on

5040-401: The core memory , which is erased when read. For input and output, the PDP-8 has a single interrupt shared by all devices, an I/O bus accessed by I/O instructions and a direct memory access (DMA) channel. The programmed I/O bus typically runs low to medium-speed peripherals, such as printers , teletypes , paper tape punches and readers, while DMA is used for cathode-ray tube screens with

5145-464: The DECstation range beyond the planned R4400-based products. Shortly prior to the release of the DEC Alpha systems, a port of OSF/1 to the DECstation was completed, but it was not commercially released. As the previously announced strategy had "fizzled", DEC representatives had reportedly "informed ULTRIX customers that they should start planning to move to Alpha workstations running OSF/1 in 1993", having

5250-528: The DECsystem 3100. Code name MIPSMATE. A pedestal uniprocessor system based on the Q-Bus . It shared many hardware options with the 3x00-series MAYFAIR VAXes , including TK70 tape drive, MS650-BA memory and DSSI disk drives. SCSI was not available except with third party add in hardware. The unit shipped with a MicroVAX diagnostic processor, which would run similar ROM diagnostics to the MicroVAX series, as well as boot

5355-527: The Digital Equipment Corporation User Society, and often came with full source listings and documentation. The three high-order bits of the 12-bit instruction word (labelled bits 0 through 2) are the operation code. For the six operations that refer to memory, bits 5 through 11 provide a seven-bit address. Bit 4, if set, says to complete the address using the five high-order bits of the program counter (PC) register, meaning that

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5460-696: The I/O buses. The I/O Controller ASIC was not introduced by the Model 240, it was first featured in the Model 100 series, but the ASIC used in the Model 240 differs by being clocked twice as high, at 25 MHz instead of 12.5 MHz. The Model 240's I/O subsystem would later be used in the DEC 3000 AXP in a modified form. DECstation systems with TURBOchannel slots could use TURBOchannel-based framebuffers, 2D graphics accelerators and 3D graphics accelerators. These options were: All PXG variants are capable of either 8-bit or 24-bit color,

5565-449: The MT ASIC implements TURBOchannel and serves as the controller. The Model 200's I/O subsystem is significantly different from the Model 240 and 260's I/O subsystem. In the Model 200, Ethernet and SCSI capabilities are provided by two integrated TURBOchannel option modules, PMAD-AA for Ethernet and PMAZ-AA for SCSI. The PMAD-AA uses an AMD 7990 LANCE (Local Area Network Controller for Ethernet), which provides 10BASE-T Ethernet. The interface

5670-432: The MT ASIC, which serves as the memory controller. The MT ASIC provides memory control and refresh, handles memory DMA and transactions, and ECC checking. The MS (Memory Strobe) ASIC provides 15 sets of memory control lines and routes memory control signals from the MT ASIC to the destination SIMM. The MS ASIC replaces 16 discrete components used in the Model 200 and also generates the 25 MHz system clock signal, replacing

5775-592: The Model 100 Series to reuse the old memory. Three TURBOchannel option slots are provided. The Model 100 Series introduces the I/O Controller ASIC (later known as the IOCTL ASIC), which interfaces the two 8-bit I/O buses to the 12.5 MHz TURBOchannel. The DECstation 200 Series are high-end workstations. Server configurations of the DECstation 500 Model 200, 240 and 260 were known as the DECsystem 5000 Model 200, 240 and 260 respectively. These systems only contain

5880-508: The Model 200 Series had a unique CPU subsystem. The Model 200's CPU subsystem is located on the KN02 system module and contains a chipset composed of the R3000 CPU, R3010 FPU and R3220 MB (six-stage write/memory buffer). Also part of the subsystem is the processor's external 64 KB instruction cache and 64 KB write-through data cache. In contrast, the Model 240's CPU subsystem is located on

5985-517: The Multiplier/Quotient (MQ) register. The EAE was an option on the original PDP-8, the 8/I, and the 8/E, but it is an integral part of the Intersil 6100 microprocessor. The PDP-8 is optimized for simplicity of design . Compared to more complex machines, unnecessary features were removed and logic is shared when possible. Instructions use autoincrement, autoclear, and indirect access to increase

6090-653: The PDP-8's emphasis on a simple instruction set and achieving multiple actions in a single instruction cycle, in order to maximize execution speed, although the newer computers have much longer instruction words. The PDP-8 used ideas from several 12-bit predecessors such as the LINC designed by W.A. Clark and C.E. Molnar , who were inspired by Seymour Cray 's CDC 160 minicomputer. The PDP-8 uses 12 bits for its word size and arithmetic (on unsigned integers from 0 to 4095 or signed integers from −2048 to +2047). However, software can do multiple-precision arithmetic . An interpreter

6195-481: The Unix workstation group, thus reportedly causing "as much of an internal uproar as it did an external one". At the end of 1992, company representatives were once again less certain about the prospects of delivering OSF/1 on the DECstation range, with the projected release in the first half of 1993 "up in the air" and under threat of being cancelled if sufficient interest were not forthcoming from software vendors. Internally,

6300-562: The accumulator to be cleared, incremented, then rotated left, leaving it set to 2. In this way, small integer constants were placed in the accumulator with a single instruction. DECsystem DECsystem was a line of server computers from Digital Equipment Corporation . They were based on MIPS architecture processors and ran DEC's version of the UNIX operating system , called ULTRIX . They ranged in size from workstation-style desktop enclosures to large pedestal cabinets. The DECSYSTEM name

6405-474: The addressed location was within the same 128 words as the instruction. If bit 4 is clear, zeroes are used, so the addressed location is within the first 128 words of memory. Bit 3 specifies indirection; if set, the address obtained as described so far points to a 12-bit value in memory that gives the actual effective address for the instruction; this way, operands can be anywhere in memory at the expense of an additional word. The JMP instruction does not operate on

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6510-561: The assembler combines them with OR to devise the actual instruction word. Many I/O devices support "microcoded" IOT instructions. Microcoded actions take place in a well-defined sequence designed to maximize the utility of many combinations. The OPR instructions come in Groups. Bits 3, 8 and 11 identify the Group of an OPR instruction, so it is impossible to combine the microcoded actions from different groups. One action (and corresponding bit) which

6615-406: The core memory. However, the I/O devices need more electronic logic to manage their own word count and transfer address registers. By the time the PDP-8/E was introduced, electronic logic had become less expensive and "one-cycle data break" became more popular. Early PDP-8 systems were shipped with no pre-installed software; each time the PDP-8 was powered up, the user hand-entered instructions using

6720-607: The current page require an extra word. Consequently, much time was spent cleverly conserving one or several words. Programmers deliberately placed code at the end of a page to achieve a free transition to the next page as PC was incremented. The PDP-8 processor defined few of the IOT instructions, but simply provided a framework. Most IOT instructions were defined by the individual I/O devices. Bits 3 through 8 of an IOT instruction select an I/O device. Some of these device addresses are standardized by convention: Instructions for device 0 affect

6825-404: The decision, driven by uncertainty about the future of the MIPS-based DECstations and ULTRIX, led to a revision of the company's strategy, with DEC promising "a production-quality version of OSF/1" with support for all of the company's Unix-based workstations and servers. Following on from the "advanced developer's kit" - this being the version offering support for only certain models - the intention

6930-405: The development of the mx binary translator to run ULTRIX MIPS program images on Alpha-based DEC OSF/1 systems. The GXemul project emulates several of these DECstation models. The original MIPS-based DECstation 3100 was followed by a cost reduced 2100. The DECstation 3100 was claimed to be the world's fastest UNIX workstation at the time. When it was introduced it was about three times as fast as

7035-544: The effect of undermining customer confidence in both the DECstation line and in ULTRIX, but also raising more serious concerns about the company's broader Unix strategy. Although introduced before DEC started to pursue a strategy based on the Advanced Computing Environment platform, the company's stated intention was that DECstation users could potentially migrate to an OSF/1-based product, potentially delivered in

7140-452: The electronics permitted a much smaller case, about the size of a bread-box. The 8/S was designed by Saul Dinman. The even later PDP-8/E is a larger, more capable computer, but further reengineered for better value. It employs faster transistor–transistor logic , in integrated circuits. The core memory was redesigned. It allows expansion with less expense because it uses the OMNIBUS in place of

7245-522: The end of the PDP-8 era, floppy disks and moving-head cartridge disk drives were popular I/O devices. Modern enthusiasts have created standard PC style IDE hard disk adapters for real and simulated PDP-8 computers. Several types of I/O are supported: A simplified, inexpensive form of DMA called "three-cycle data break" is supported; this requires the assistance of the processor. The "data break" method moves some of common logic needed to implement DMA I/O from each I/O device into one common copy of

7350-456: The faster CPU module and the slower 12.5 MHz system module. The CPUCTL ASIC also implements a 12.5 MHz TURBOchannel that serves as the system interconnect. The second model is a revised version of the first module with a 20 or 25 MHz R3000A and R3010 that used plastic packaging, whereas the previous model used ceramic packaging. The third model contains a R4000 microprocessor with internal instruction and data caches complemented by

7455-422: The form of SCO Open Desktop for the platform, offering binary compatibility with the existing ULTRIX system. DEC even suggested that Windows NT would be available for DECstation models, and Microsoft demonstrated NT running on Personal DECstation models. However, throughout the lifespan of the Alpha design activity, it had long been envisaged that VAX and MIPS binaries would be made to run on Alpha systems, leading to

7560-437: The front. The system logic was contained on two printed circuit boards , the base system module, which contained the majority of the logic, and the CPU module, which contained the processor. Initial pricing for these 5000 series models started at $ 3,995 for a diskless 5000/20 with 8 MB of RAM and 17-inch greyscale display. There were three models of the CPU module, which contains the CPU subsystem. The first model contains

7665-520: The interface, a BNC ThinWire Ethernet connector. A 32 768 word × 16-bit (64 KB) network buffer constructed out of SRAMs is provided to improve performance. A 32 word by 8-bit Ethernet Station Address ROM (ESAR) provides the MAC address . It is mounted in a DIP socket and is removable. The 5 MB/s single-ended SCSI interface is provided by a DC7061 SII gate array with a 64 K by 16-bit (128 KB) SCSI buffer used to improve performance. The SCSI interface

7770-417: The lack of expansion capabilities by providing the TURBOchannel Interconnect. The DECstation 5000 systems are also ARC (Advanced RISC Computing) compatible. The last DECstation models focused on increased component integration by using more custom ASICs to reduce the number of discrete components. This began with the DECstation 5000 Model 240, which replaced discrete components with LSI ASICs and ended with

7875-451: The last model, the DECstation 5000 Model 260, which used a single VLSI ASIC for much of the control logic. Packaged DECstation 5000 systems were sometimes suffixed with two or three letters. These letters refer to what graphics option the system has. The DECstation 3100 and 2100 uses a R2000 processor, a R2010 floating point coprocessor and four R2020 write buffers. The R2000 uses an external 64 KB direct-mapped instruction cache and

7980-462: The logic within the processor. "Data break" places the processor in charge of maintaining the DMA address and word count registers. In three successive memory cycles, the processor updates the word count, updates the transfer address, and stores or retrieves the actual I/O data word. One-cycle data break effectively triples the DMA transfer rate because only the target data needed to be transferred to and from

8085-469: The marketing group for the DECstation had been able to convince DEC's product strategy group that the loss in sales in failing to offer OSF/1 on the hardware would exceed the research and development costs involved in making it available, but company-wide spending cuts threatened such projects. Subsequent indications from DEC confirmed, without further elaboration, the cancellation of the product alongside increasing uncertainty around further hardware upgrades to

8190-565: The memory and communicates with the CPU subsystem via the TURBOchannel bus. Expansion is provided by two TURBOchannel slots, each with 64 MB of physical address space. The Personal DECstation features an integrated 8-bit color frame buffer capable of a resolution of 1024 × 768 at a refresh rate of 72 Hz. The frame buffer consists of 1 MB of VRAM organized as 262,144 32-bit words, with each 32-bit word containing four 8-bit pixels. The frame buffer uses an INMOS IMS G332 RAMDAC with

8295-416: The memory system is byte-parity protected. The monochrome framebuffer are implemented with a 256 KB VFB01 SIMM and the color framebuffer, a 1 MB VBF02 SIMM. If one of these framebuffer SIMMs are not present, the framebuffer cannot be used. The SIMM slots were rated for 25 removal and insertion cycles, with five being the recommended limit. Graphics capability was provided by two frame buffer modules,

8400-482: The monochrome and color frame buffer. The monochrome frame buffer supports 1-bit color and a resolution of 1024 × 864 pixels, while the color frame buffer supports 8-bit color and the same resolution as the monochrome frame buffer. Both frame buffers use the Brooktree Bt478 RAMDAC with three 256-entry, 8-bit color maps. The hardware cursor is generated by DC503 PCC (Programmable Cursor Chip), which can provide

8505-489: The offering failed. Intersil sold the integrated circuits commercially through 1982 as the Intersil 6100 family. By virtue of their CMOS technology they had low power requirements and were used in some embedded military systems. The chief engineer who designed the initial version of the PDP-8 was Edson de Castro , who later founded Data General . The PDP-8 combines low cost, simplicity, expandability, and careful engineering for value. The greatest historical significance

8610-604: The operation of the Fuel Handling Machine while it was used to remove fuel from the reactor core and decommission the plant. It included a simulated paper tape loader and front panel. The I/O systems underwent huge changes during the PDP-8 era. Early PDP-8 models use a front panel interface, a paper-tape reader and a teletype printer with an optional paper-tape punch. Over time, I/O systems such as magnetic tape , RS-232 and current loop dumb terminals , punched card readers, and fixed-head disks were added. Toward

8715-693: The original PDP-8. A basic 8/S sold for under $ 10,000, the first machine to reach that milestone. Later systems (the PDP-8/I and /L, the PDP-8/E, /F, and /M, and the PDP-8/A) returned to a faster, fully parallel implementation but use much less costly transistor–transistor logic (TTL) MSI logic. Most surviving PDP-8s are from this era. The PDP-8/E is common, and well-regarded because many types of I/O devices were available for it. The last commercial PDP-8 models introduced in 1979 are called "CMOS-8s", based on CMOS microprocessors. They were not priced competitively, and

8820-603: The presence of two CPU drawers in a rack simply meant that there were two separate systems. The mass storage drawers, in such a case, would be divided between the CPU drawers, with a minimum of one per a CPU drawer. There are two models of mass storage drawers. One model may contain one to four 5.25-inch full-height non-removable, one 5.25-inch full-height removable or non-removable and two 5.25-inch half-height removable devices. The other model may contain one to five 5.25-inch full-height non-removable, one 5.25-inch removable and two 5.25-inch half-height removable devices. In both models,

8925-420: The processor as a whole. For example, ION (6001) enables interrupt processing, and IOFF (6002) disables it. Bits 9 through 11 of an IOT instruction select the function(s) the device performs. Simple devices (such as the paper tape reader and punch and the console keyboard and printer) use the bits in standard ways: These operations take place in a well-defined order that gives useful results if more than one bit

9030-571: The project's inception was whether or not DEC could sustain, grow, and compete with an architecture it did not invent or own (manage). As the core advocates later left the company, the MIPS-based line of computers was shut down in favor of the Alpha-based computers, a DEC invented and owned architecture, descended from the PRISM development work. The first generation of commercially marketed DEC Alpha systems,

9135-463: The required mechanics, as opposed to setting out the algorithm. For example, subtracting a number involves computing its two's complement then adding it; writing a conditional jump involves writing a conditional skip around the jump, the skip coding the condition negative to the one desired. Some ambitious programming projects failed to fit in memory or developed design defects that could not be solved. For example, as noted below , inadvertent recursion of

9240-406: The same DRAMs, allowing the Model 200 Series to achieve an effective maximum bandwidth of 100 MB/s. An optional 1 MB NVRAM module that provides a disk cache to improve performance can be installed in one of the SIMM slots (slot 14, the SIMM slot closest to the front edge of the system module). The module uses a battery to prevent data from being lost in case of power failure. The module

9345-436: The software's speed, reduce memory use, and substitute inexpensive memory for expensive registers. Because of their simplicity, early PDP-8 models were less expensive than most other commercially available computers. However, they used costly production methods often used for prototypes. They used thousands of very small, standardized logic-modules, with gold connectors, integrated by a costly, complex wire-wrapped backplane in

9450-418: The special property of auto-incrementing preceding any indirect reference through them.) The standard assembler places constant values for arithmetic in the current page. Likewise, cross-page jumps and subroutine calls use an indirect address in the current page. It was important to write routines to fit within 128-word pages, or to arrange routines to minimize page transitions, as references and jumps outside

9555-470: The subsystem to the TURBOchannel interconnect. The DECstation 5000 Model 100 Series, code named "3MIN", are mid-range workstations. Early models used a chipset consisting of a R3000A CPU and a R3010 CPU on 3- by 5-inch daughter card that plugs into a connector on the system module. The Model 150 replaces the R3000A and R3010 with a single R4000 with an integrated FPU. The Model 120 and 125 have two external caches,

9660-486: The system module that can hold 8 to 480 MB of memory. Proprietary 128-pin memory array modules (SIMMs) with capacities of 8 MB (39 1 Mbit DRAM chips) or 32 MB (39 4 Mbit DRAM chips) are used. All SIMMs installed in a system must be of the same size. If 8 MB SIMMs are used, the system may contain 8 to 120 MB of memory. If 32 MB SIMMs are used, the system may contain 32 to 480 MB of memory. The memory subsystem operates at 25 MHz and

9765-453: The system module. The system module is located on the left of the enclosure and the power supply, which takes up a fourth of the space inside the enclosure, is located on the left. The Personal DECstation 5000 Series are entry-level workstations, code named "MAXine". The Personal DECstation uses a low-profile desktop case, which contained a power supply on the left and two mounts for two fixed drives, or one fixed drive and one diskette drive, at

9870-605: The systems family was to also employ a truly RISC-based architecture when compared to the heavier and very CISC VAX or the then still under development PRISM architectures. At the time DEC was mostly known for their CISC systems including the successful PDP-11 and VAX lines. Several architectures were considered from Intel , Motorola and others but the group quickly selected the MIPS line of microprocessors. The (early) MIPS microprocessors supported both big- and little-endian modes (configured during hardware reset). Little-endian mode

9975-457: The tape based MicroVAX Diagnostic TK70 tape. Once the console transferred control of the computer to the MIPS processor the MicroVAX sat essentially unused until the next boot. Code name MIPSFAIR. A pedestal uniprocessor system based on the Q-Bus . It replaced the DECsystem 5400. The 5500 came with native SCSI support, as well as support for DSSI disk drives. Code name MIPSFAIR-2. The DECsystem 5500

10080-550: The wire-wrapped backplane on earlier models. (A personal account of the development of the PDP-8/E can be read on the Engineering and Technology History Wiki. ) The total sales figure for the PDP-8 family has been estimated at over 300,000 machines. The following models were manufactured: The PDP-8 is readily emulated , as its instruction set is much simpler than modern architectures. Enthusiasts have created entire PDP-8s using single FPGA devices. Several software simulations of

10185-400: Was also available. TSS-8 allows multiple users to log into the system via 110-baud terminals, and edit, compile and debug programs. Languages include a special version of BASIC, a FORTRAN subset similar to FORTRAN-1 (no user-written subroutines or functions), an ALGOL subset, FOCAL, and an assembler called PAL-D. A fair amount of user-donated software for the PDP-8 was available from DECUS ,

10290-952: Was also used for later models of the PDP-10 , namely the DECSYSTEM-10 and DECSYSTEM-20 series. Identical to the DECstation 3100 , but was intended to be used as a multiuser system. It was announced in early May 1989 at the UniForum exhibition in San Francisco. It was shipped in June 1989. Code name PMAX. Rebranded Personal DECstation 5000 Series without any graphics. Code name MAXINE. Rebranded DECstation 5000 Model 100 Series without any graphics. Codename 3MIN. Rebranded DECstation 5000 Model 200 Series without any graphics. Code name 3MAX. (5000/260 3MAX+). A desktop uniprocessor entry-level server. It replaced

10395-569: Was available for floating point operations, for example, that uses a 36-bit floating point representation with a two-word (24-bit) significand (mantissa) and one-word exponent. Subject to speed and memory limitations, the PDP-8 can perform calculations similar to more expensive contemporary electronic computers, such as the IBM 1130 and various models of the IBM System/360 , while being easier to interface with external devices. The memory address space

10500-494: Was chosen both to match the byte ordering of VAX-based systems and the growing number of Intel-based PCs and computers. In contrast to the VAX and the later DEC Alpha architectures, the DECstation 3100 and family were specifically designed and built to run a UNIX system, ULTRIX , and no version of the VMS operating system was ever released for DECstations. One of the issues being debated at

10605-553: Was considered to offer "no performance advantage over main memory" and, in the context of the X server implemented by Digital, would have complicated the memory management involved. The frame buffers are not parity-protected, unlike the rest of the system memory. A DB15 male connector is used for video. The connector uses RS343A/RS170 compatible signals. These DECstations have onboard 10 Mbit/s Ethernet provided by an AMD 7990 LANCE (Local Area Network Controller for Ethernet) and an AMD 7992 SIA (Serial Interface Adapter), which implements

10710-400: Was that the PDP-8's low cost and high volume made a computer available to many new customers for many new uses. Its continuing significance is as a historical example of value-engineered computer design. The low complexity brought other costs. It made programming cumbersome, as is seen in the examples in this article and from the discussion of "pages" and "fields". Much of one's code performed

10815-461: Was the DEC 3000 Model 800S AXP packaged in a similar rack-mountable enclosure. The DECstation system module is repackaged in a CPU drawer, which is mounted in a rack with a mounting kit which permits the drawer to be slid in and out. The CPU module also contained an integrated TURBOchannel Extender, the power supply and a blower, which cooled the system. However, as the system module that these systems use does not feature multiprocessing capabilities,

10920-469: Was the fruit of an advanced development skunkworks project carried out in DEC's Palo Alto Hamilton Ave facility. Known as the PMAX project, its focus was to produce a computer systems family with the economics and performance to compete against the likes of Sun Microsystems and other RISC-based UNIX platforms of the day. The brainchild of James Billmaier , Mario Pagliaro, Armando Stettner and Joseph DiNucci ,

11025-430: Was to produce an "end-user release" of OSF/1 during 1993 for R2000-, R3000- and R4000-based models, offering compatibility with OSF/1 on Alpha. Alongside such plans, DEC would also continue to support ULTRIX on its R4000-based systems. The strategic confusion was blamed on power struggles within DEC, with the decision made to abandon further OSF/1 work on DECstations being attributed to an executive having gained control over

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