DECsystem was a line of server computers from Digital Equipment Corporation . They were based on MIPS architecture processors and ran DEC's version of the UNIX operating system , called ULTRIX . They ranged in size from workstation-style desktop enclosures to large pedestal cabinets.
86-970: The DECSYSTEM name was also used for later models of the PDP-10 , namely the DECSYSTEM-10 and DECSYSTEM-20 series. Identical to the DECstation 3100 , but was intended to be used as a multiuser system. It was announced in early May 1989 at the UniForum exhibition in San Francisco. It was shipped in June 1989. Code name PMAX. Rebranded Personal DECstation 5000 Series without any graphics. Code name MAXINE. Rebranded DECstation 5000 Model 100 Series without any graphics. Codename 3MIN. Rebranded DECstation 5000 Model 200 Series without any graphics. Code name 3MAX. (5000/260 3MAX+). A desktop uniprocessor entry-level server. It replaced
172-558: A mainframe or big iron , is a computer used primarily by large organizations for critical applications like bulk data processing for tasks such as censuses , industry and consumer statistics , enterprise resource planning , and large-scale transaction processing . A mainframe computer is large but not as large as a supercomputer and has more processing power than some other classes of computers, such as minicomputers , servers , workstations , and personal computers . Most large-scale computer-system architectures were established in
258-458: A 400 W power supply is located at the rear of the drawer. The H9A00 enclosure, a 19-inch rack , contains a minimum of one CPU drawer and one mass storage drawer. A power controller at the bottom of the enclosure distributed power to the CPU and mass storage drawers. The rack can contain a maximum of two CPU drawers and four mass storage drawers. The DECsystem 5900 has a width of 61 cm (24 in),
344-567: A consequence of the symmetric design of the instruction set, it contains several no-ops such as JUMP. For example, JUMPN A,LOC jumps to the address LOC if the contents of register A is non-zero. There are also conditional jumps based on the processor's condition register using the JRST instruction. On the KA10 and KI10, JRST is faster than JUMPA, so the standard unconditional jump is JRST. The conditional skip operations compare register and memory contents and skip
430-584: A control processor. The KS10 design was crippled to be a Model A even though most of the necessary data paths needed to support the Model B architecture are present. This was no doubt intended to segment the market , but it greatly shortened the KS10's product life. The KS system uses a similar boot procedure to the KL10. The 8080 control processor loads the microcode from an RM03, RM80, or RP06 disk or magnetic tape and then starts
516-461: A device number, and 10 through 12 the instruction opcode. In both formats, bits 13 through 35 are used to form the "effective address", E. Bits 18 through 35 contain a numerical constant address, Y. This address may be modified by adding the 18-bit value in a register, X, the register number indicated in bits 14 to 17. If these are set to zero, no indexing is used, meaning register 0 cannot be used for indexing. Bit 13, I, indicates indirection, meaning
602-416: A device set to level 0 will not stop the processor even if it does raise an interrupt. Each device channel has two memory locations associated with it, one at 40+2N and the other at 41+2N, where N is the channel number. Thus, channel 1 uses locations 42 and 43. When the interrupt is received and accepted, meaning no higher-priority interrupt is already running, the system stops at the next memory read part of
688-613: A fashion similar to the BLK commands. Only the right 18 bits are tested in CONSZ. A second use of the CONO instruction is to set the device's priority level for interrupt handling. There are three bits in the CONO instruction, 33 through 35, allowing the device to be set to level 0 through 7. Level 1 is the highest, meaning that if two devices raise an interrupt at the same time, the lowest-numbered device will begin processing. Level 0 means "no interrupts", so
774-449: A fraction of the acquisition price and offer local users much greater control over their own systems given the IT policies and practices at that time. Terminals used for interacting with mainframe systems were gradually replaced by personal computers . Consequently, demand plummeted and new mainframe installations were restricted mainly to financial services and government. In the early 1990s, there
860-469: A height of 170 cm (67 in), a depth of 86.4 cm (34.0 in) and a weight of 265 to 485 kg (584 to 1,069 lb) depending on the configuration. PDP-10 Digital Equipment Corporation (DEC)'s PDP-10 , later marketed as the DECsystem-10 , is a mainframe computer family manufactured beginning in 1966 and discontinued in 1983. 1970s models and beyond were marketed under
946-539: A level of sophistication not usually available with most server solutions. Modern mainframes, notably the IBM Z servers, offer two levels of virtualization : logical partitions ( LPARs , via the PR/SM facility) and virtual machines (via the z/VM operating system). Many mainframe customers run two machines: one in their primary data center and one in their backup data center —fully active, partially active, or on standby—in case there
SECTION 10
#17328595922811032-405: A maximum main memory capacity (both virtual and physical) of 256 kilowords (equivalent to 1152 kilobytes ); the minimum main memory required is 16 kilowords. As supplied by DEC, it did not include paging hardware; memory management consists of two sets of protection and relocation registers, called base and bounds registers. This allows each half of a user's address space to be limited to
1118-434: A reference to the anticipated Year 2000 problem (Y2K). That trend started to turn around in the late 1990s as corporations found new uses for their existing mainframes and as the price of data networking collapsed in most parts of the world, encouraging trends toward more centralized computing. The growth of e-business also dramatically increased the number of back-end transactions processed by mainframe software as well as
1204-529: A semi-automated manufacturing process. Its cycle time is 1 μs and its add time 2.1 μs. In 1973, the KA10 was replaced by the KI10, which uses transistor–transistor logic (TTL) SSI . This was joined in 1975 by the higher-performance KL10 (later faster variants), which is built from emitter-coupled logic (ECL), microprogrammed , and has cache memory. The KL10's performance was about 1 megaflops using 36-bit floating point numbers on matrix row reduction. It
1290-536: A set section of main memory , designated by the base physical address and size. This allows the model of separate read-only shareable code segment (normally the high segment) and read-write data/ stack segment (normally the low segment) used by TOPS-10 and later adopted by Unix . Some KA10 machines, first at MIT, and later at Bolt, Beranek and Newman (BBN), were modified to add virtual memory and support for demand paging , and more physical memory. The KA10 weighs about 1,920 pounds (870 kg). The 10/50
1376-407: A single mainframe can replace higher-functioning hardware services available to conventional servers . While mainframes pioneered this capability, virtualization is now available on most families of computer systems, though not always to the same degree or level of sophistication. Mainframes can add or hot swap system capacity without disrupting system function, with specificity and granularity to
1462-464: A special format of indirect word to extract and store arbitrary-sized bit fields, possibly advancing a pointer to the next unit. The PDP-10 does not use memory-mapped devices , in contrast to the PDP-11 and later DEC machines. A separate set of instructions is used to move data to and from devices defined by a device number in the instruction. Bits 3 to 9 contain the device number, with the 7 bits allowing
1548-470: A total of 128 devices. Instructions allow for the movement of data to and from devices in word-at-a-time (DATAO and DATAI) or block-at-a-time (BLKO, BLKI). In block mode, the value pointed to by E is a word in memory that is split in two, the right 18 bits indicate a starting address in memory where the data is located (or written into) and the left 18 bits are a counter. The block instructions increment both values every time they are called, thereby increasing
1634-882: A user process a "high" and a "low" memory: addresses with a 0 top bit use one base register and those with a 1 use another. Each segment is contiguous. Later architectures have paged memory access, allowing non-contiguous address spaces. The CPU's general-purpose registers can also be addressed as memory locations 0–15. There are three main classes of general instructions: arithmetic, logical, and move; conditional jump; conditional skip (which may have side effects). There are also several smaller classes. The arithmetic, logical, and move operations include variants which operate immediate-to-register, memory-to-register, register-to-memory, register-and-memory-to-both or memory-to-memory. Since registers may be addressed as part of memory, register-to-register operations are also defined. (Not all variants are useful, though they are well-defined.) For example,
1720-451: Is 30 bits, divided into a 12-bit section number at the bottom of the left 18 bits and an 18-bit offset within that section in the right 18 bits. A register can contain either a "local index", with an 18-bit unsigned displacement or local address in the right 18 bits, or a "global index", with a 30-bit unsigned displacement or global address in the right 30 bits. An indirect word can either be a "local indirect word", with its uppermost bit set,
1806-732: Is a catastrophe affecting the first building. Test, development, training, and production workload for applications and databases can run on a single machine, except for extremely large demands where the capacity of one machine might be limiting. Such a two-mainframe installation can support continuous business service, avoiding both planned and unplanned outages. In practice, many customers use multiple mainframes linked either by Parallel Sysplex and shared DASD (in IBM's case), or with shared, geographically dispersed storage provided by EMC or Hitachi. Mainframes are designed to handle very high volume input and output (I/O) and emphasize throughput computing. Since
SECTION 20
#17328595922811892-450: Is also spurring major mainframe investments to solve exceptionally difficult computing problems, e.g. providing unified, extremely high volume online transaction processing databases for 1 billion consumers across multiple industries (banking, insurance, credit reporting, government services, etc.) In late 2000, IBM introduced 64-bit z/Architecture , acquired numerous software companies such as Cognos and introduced those software products to
1978-634: Is being refreshed. In the late 1950s, mainframes had only a rudimentary interactive interface (the console) and used sets of punched cards , paper tape , or magnetic tape to transfer data and programs. They operated in batch mode to support back office functions such as payroll and customer billing, most of which were based on repeated tape-based sorting and merging operations followed by line printing to preprinted continuous stationery . When interactive user terminals were introduced, they were used almost exclusively for applications (e.g. airline booking ) rather than program development. However, in 1961
2064-757: Is dependent on its ability to scale, support mixed workloads, reduce labor costs, deliver uninterrupted service for critical business applications, and several other risk-adjusted cost factors. Mainframes also have execution integrity characteristics for fault tolerant computing. For example, z900, z990, System z9, and System z10 servers effectively execute result-oriented instructions twice, compare results, arbitrate between any differences (through instruction retry and failure isolation), then shift workloads "in flight" to functioning processors, including spares, without any impact to operating systems, applications, or users. This hardware-level feature, also found in HP's NonStop systems,
2150-421: Is known as lock-stepping, because both processors take their "steps" (i.e. instructions) together. Not all applications absolutely need the assured integrity that these systems provide, but many do, such as financial transaction processing. IBM , with the IBM Z series, continues to be a major manufacturer in the mainframe market. In 2000, Hitachi co-developed the zSeries z900 with IBM to share expenses, and
2236-509: Is shipped in a BA430 enclosure, which provides a 12-slot backplane and room for four mass storage devices. The base system contains the following: The DECsystem 5800 Series are high-end multiprocessor systems. The series comprised the DECsystem 5810, 5820, 5830, and 5840, with the third digit referring to the number of processors. These systems can be considered to be the MIPS/RISC alternatives of
2322-476: Is split in half; the right 18 bits contains the program counter and the left 13 bits contains the processor status flags , with five zeros between the two sections. The condition register bits, which record the results of arithmetic operations ( e.g. overflow), can be accessed by only a few instructions. In the original KA-10 systems, these registers are simply the first 16 words of main memory . The "fast registers" hardware option implements them as registers in
2408-493: The Telum . Unisys produces code compatible mainframe systems that range from laptops to cabinet-sized mainframes that use homegrown CPUs as well as Xeon processors. Furthermore, there exists a market for software applications to manage the performance of mainframe implementations. In addition to IBM, significant market competitors include BMC and Precisely ; former competitors include Compuware and CA Technologies . Starting in
2494-601: The VAX 6000 operating the XMI and BI bus. The 5810 and 5820, using 25 MHz R3000 microprocessors and R3010 floating-point coprocessors, were introduced on 11 July 1989. Code name ISIS. The DECsystem 5900 and DECsystem 5900/260 are rack-mounted DECstation 5000 Model 240 and DECstation Model 260 workstations, respectively, positioned as mid-range servers by Digital. The DECsystem 5900 was introduced in early December 1991. Both models were discontinued on 28 January 1994. Their intended replacement
2580-404: The instruction cycle and instead begins processing at the address stored in the first of those two locations. It is up to the interrupt handler to turn off the interrupt level when it is complete, which it can do by running a CONO, DATA or BLK instruction. Two of the device numbers are set aside for special purposes. Device 0 is the computer's front-panel console; reading that device retrieves
2666-684: The 1960s, but they continue to evolve. Mainframe computers are often used as servers. The term mainframe was derived from the large cabinet, called a main frame , that housed the central processing unit and main memory of early computers. Later, the term mainframe was used to distinguish high-end commercial computers from less powerful machines. Modern mainframe design is characterized less by raw computational speed and more by: The high stability and reliability of mainframes enable these machines to run uninterrupted for very long periods of time, with mean time between failures (MTBF) measured in decades. Mainframes have high availability , one of
DECsystem - Misplaced Pages Continue
2752-504: The 1980s, many mainframes supported general purpose graphic display terminals, and terminal emulation, but not graphical user interfaces. This form of end-user computing became obsolete in the 1990s due to the advent of personal computers provided with GUIs . After 2000, modern mainframes partially or entirely phased out classic " green screen " and color display terminal access for end-users in favour of Web-style user interfaces. The infrastructure requirements were drastically reduced during
2838-595: The 2010s, cloud computing is now a less expensive, more scalable alternative. Several manufacturers and their successors produced mainframe computers from the 1950s until the early 21st century, with gradually decreasing numbers and a gradual transition to simulation on Intel chips rather than proprietary hardware. The US group of manufacturers was first known as " IBM and the Seven Dwarfs ": usually Burroughs , UNIVAC , NCR , Control Data , Honeywell , General Electric and RCA , although some lists varied. Later, with
2924-688: The 20xx series KL machines is based on a DEC bus design called the Massbus . While many attributed the success of the PDP-11 to DEC's decision to make the PDP-11 Unibus an open architecture, DEC reverted to prior philosophy with the KL, making Massbus both unique and proprietary. Consequently, there were no aftermarket peripheral manufacturers who made devices for the Massbus, and DEC chose to price their own Massbus devices, notably
3010-890: The 64-bit IBM Z CMOS servers have nothing physically in common with the older systems. Notable manufacturers outside the US were Siemens and Telefunken in Germany , ICL in the United Kingdom , Olivetti in Italy, and Fujitsu , Hitachi , Oki , and NEC in Japan . The Soviet Union and Warsaw Pact countries manufactured close copies of IBM mainframes during the Cold War ; the BESM series and Strela are examples of independently designed Soviet computers. Elwro in Poland
3096-555: The ADD operation has as variants ADDI (add an 18-bit I mmediate constant to a register), ADDM (add register contents to a M emory location), ADDB (add to B oth, that is, add register contents to memory and also put the result in the register). A more elaborate example is HLROM ( H alf L eft to R ight, O nes to M emory), which takes the Left half of the register contents, places them in the Right half of
3182-530: The AN20 IMP interface was an I/O bus device. Both could run either TOPS-10 or TOPS-20 microcode and thus the corresponding operating system. The later Model B version of the 2060 processors removes the 256 kilo word limit on the virtual address space by supporting up to 32 "sections" of up to 256 kilowords each, along with substantial changes to the instruction set. The two versions are effectively different CPUs. The first operating system that takes advantage of
3268-482: The CPU, still addressable as the first 16 words of memory. Some software takes advantage of this by using the registers as an instruction cache by loading code into the registers and then jumping to the appropriate address; this is used, for example, in Maclisp to implement one version of the garbage collector . Later models all have registers in the CPU. There are two operational modes, supervisor and user mode. Besides
3354-528: The DECsystem 3100. Code name MIPSMATE. A pedestal uniprocessor system based on the Q-Bus . It shared many hardware options with the 3x00-series MAYFAIR VAXes , including TK70 tape drive, MS650-BA memory and DSSI disk drives. SCSI was not available except with third party add in hardware. The unit shipped with a MicroVAX diagnostic processor, which would run similar ROM diagnostics to the MicroVAX series, as well as boot
3440-601: The DECsystem-10 name, especially as the TOPS-10 operating system became widely used. The PDP-10's architecture is almost identical to that of DEC's earlier PDP-6 , sharing the same 36-bit word length and slightly extending the instruction set. The main difference was a greatly improved hardware implementation. Some aspects of the instruction set are unusual, most notably the byte instructions, which operate on bit fields of any size from 1 to 36 bits inclusive, according to
3526-542: The Japanese market. The amount of vendor investment in mainframe development varies with market share. Fujitsu and Hitachi both continue to use custom S/390-compatible processors, as well as other CPUs (including POWER and Xeon) for lower-end systems. Bull uses a mixture of Itanium and Xeon processors. NEC uses Xeon processors for its low-end ACOS-2 line, but develops the custom NOAH-6 processor for its high-end ACOS-4 series. IBM also develops custom processors in-house, such as
DECsystem - Misplaced Pages Continue
3612-588: The KL-10; extended addressing, which changes the process of generating the effective address of an instruction, is briefly discussed at the end. Generally, the system has 36-bit words and instructions, and 18-bit addresses. Note that the bit numbering order is different from some other DEC processors, and many newer processors. There are 16 general-purpose, 36-bit registers. The right half of these registers (other than register 0) may be used for indexing. A few instructions operate on pairs of registers. The "PC Word" register
3698-610: The Model B's capabilities is TOPS-20 release 3, and user mode extended addressing is offered in TOPS-20 release 4. TOPS-20 versions after release 4.1 only run on a Model B. TOPS-10 versions 7.02 and 7.03 also use extended addressing when run on a 1090 (or 1091) Model B processor running TOPS-20 microcode. The final upgrade to the KL10 was the MCA25 upgrade of a 2060 to 2065 (or a 1091 to 1095), which gave some performance increases for programs which run in multiple sections. The I/O architecture of
3784-467: The PDP-11 to start the main processor, which is typically booted from the same RP06 disk drive as the PDP-11. The PDP-11 performs watchdog functions once the main processor is running. Communication with IBM mainframes, including Remote Job Entry (RJE), was accomplished via a DN61 or DN-64 front-end processor, using a PDP-11/40 or PDP-11/34a. The KS10 is a lower-cost PDP-10 built using AMD 2901 bit-slice chips, with an Intel 8080A microprocessor as
3870-535: The RP06 disk drive, at a substantial premium above comparable IBM-compatible devices. CompuServe for one, designed its own alternative disk controller that could operate on the Massbus, but connect to IBM style 3330 disk subsystems. The KL class machines have a PDP-11/40 front-end processor for system start-up and monitoring. The PDP-11 is booted from a dual-ported RP06 disk drive (or alternatively from an 8" floppy disk drive or DECtape ), and then commands can be given to
3956-422: The aforementioned tape drives could read/write from/to 200 BPI , 556 BPI and 800 BPI IBM-compatible tapes. The TM10 Magtape controller was available in two submodels: From the first PDP-6s to the KL-10 and KS-10, the user-mode instruction set architecture is largely the same. This section covers that architecture. The only major change to the architecture is the addition of multi-section extended addressing in
4042-588: The architecture are two's complement 36-bit integer arithmetic (including bitwise operations), 36-bit floating-point, and halfwords. Extended, 72-bit, floating point is supported through special instructions designed to be used in multi-instruction sequences. Byte pointers are supported by special instructions. A word structured as a "count" half and a "pointer" half facilitates the use of bounded regions of memory, notably stacks . Instructions are stored in 36-bit words. There are two formats, general instructions and input/output instructions. In general instructions,
4128-524: The back-office engines behind the world's financial markets and much of global commerce". As of 2010 , while mainframe technology represented less than 3% of IBM's revenues, it "continue[d] to play an outsized role in Big Blue's results". IBM has continued to launch new generations of mainframes: the IBM z13 in 2015, the z14 in 2017, the z15 in 2019, and the z16 in 2022, the latter featuring among other things an "integrated on-chip AI accelerator" and
4214-445: The corresponding bits in the left half of register A. If all those bits are E qual to zero, skip the next instruction; and in any case, replace those bits by their Boolean complement. Some smaller instruction classes include the shift/rotate instructions and the procedure call instructions. Particularly notable are the stack instructions PUSH and POP, and the corresponding stack call instructions PUSHJ and POPJ. The byte instructions use
4300-432: The counter as well as moving to the next location in memory. It then performs a DATAO or DATAI. Finally, it checks the counter side of the value at E, if it is non-zero, it skips the next instruction. If it is zero, it performs the next instruction, normally a JUMP back to the top of the loop. The BLK instructions are effectively small programs that loop over a DATA and increment instructions, but by having this implemented in
4386-592: The departure of General Electric and RCA, it was referred to as IBM and the BUNCH . IBM's dominance grew out of their 700/7000 series and, later, the development of the 360 series mainframes. The latter architecture has continued to evolve into their current zSeries mainframes which, along with the then Burroughs and Sperry (now Unisys ) MCP -based and OS1100 mainframes, are among the few mainframe architectures still extant that can trace their roots to this early period. While IBM's zSeries can still run 24-bit System/360 code,
SECTION 50
#17328595922814472-473: The difference in memory referencing described above, supervisor-mode programs can execute input/output operations. Communication from user-mode to supervisor-mode is done through Unimplemented User Operations (UUOs): instructions which are not defined by the hardware, and are trapped by the supervisor. This mechanism is also used to emulate operations which may not have hardware implementations in cheaper models. The major datatypes which are directly supported by
4558-611: The early ARPANET . For these reasons, the PDP-10 looms large in early hacker folklore . Projects to extend the PDP-10 line were eclipsed by the success of the unrelated VAX superminicomputer , and the cancellation of the PDP-10 line was announced in 1983. According to reports, DEC sold "about 1500 DECsystem-10s by the end of 1980." The original PDP-10 processor is the KA10, introduced in 1968. It uses discrete transistors packaged in DEC's Flip-Chip technology, with backplanes wire wrapped via
4644-558: The early 1990s, many supercomputers were based on a mainframe architecture with supercomputing extensions. An example of such a system is the HITAC S-3800 , which was instruction-set compatible with IBM System/370 mainframes, and could run the Hitachi VOS3 operating system (a fork of IBM MVS ). The S-3800 therefore can be seen as being both simultaneously a supercomputer and also an IBM-compatible mainframe. In 2007, an amalgamation of
4730-748: The first academic, general-purpose timesharing system that supported software development, CTSS , was released at MIT on an IBM 709 , later 7090 and 7094. Typewriter and Teletype devices were common control consoles for system operators through the early 1970s, although ultimately supplanted by keyboard / display devices. By the early 1970s, many mainframes acquired interactive user terminals operating as timesharing computers, supporting hundreds of users simultaneously along with batch processing. Users gained access through keyboard/typewriter terminals and later character-mode text terminal CRT displays with integral keyboards, or finally from personal computers equipped with terminal emulation software. By
4816-559: The first time. IBM received the vast majority of mainframe revenue. During the 1980s, minicomputer -based systems grew more sophisticated and were able to displace the lower end of the mainframes. These computers, sometimes called departmental computers , were typified by the Digital Equipment Corporation VAX series. In 1991, AT&T Corporation briefly owned NCR. During the same period, companies found that servers based on microcomputer designs could be deployed at
4902-476: The general definition of a byte as a contiguous sequence of a fixed number of bits . The PDP-10 was found in many university computing facilities and research labs during the 1970s, the most notable being Harvard University 's Aiken Computation Laboratory, MIT 's AI Lab and Project MAC , Stanford 's SAIL , Computer Center Corporation (CCC), ETH (ZIR), and Carnegie Mellon University . Its main operating systems , TOPS-10 and TENEX , were used to build out
4988-556: The indirect bit is 1, the value at E is fetched and the effective address calculation is repeated. If I is 1 in the stored value at E in memory, the system will then indirect through that address as well, possibly following many such steps. This process continues until an indirect word with a zero indirect bit is reached. Indirection of this sort was a common feature of processor designs of this era. In supervisor mode, addresses correspond directly to physical memory. In user mode, addresses are translated to physical memory. Earlier models give
5074-706: The late 1950s, mainframe designs have included subsidiary hardware (called channels or peripheral processors ) which manage the I/O devices, leaving the CPU free to deal only with high-speed memory. It is common in mainframe shops to deal with massive databases and files. Gigabyte to terabyte -size record files are not unusual. Compared to a typical PC, mainframes commonly have hundreds to thousands of times as much data storage online, and can access it reasonably quickly. Other server families also offload I/O processing and emphasize throughput computing. Mainframe return on investment (ROI), like any other computing platform,
5160-726: The latest Hitachi AP10000 models are made by IBM. Unisys manufactures ClearPath Libra mainframes, based on earlier Burroughs MCP products and ClearPath Dorado mainframes based on Sperry Univac OS 1100 product lines. Hewlett Packard Enterprise sells its unique NonStop systems, which it acquired with Tandem Computers and which some analysts classify as mainframes. Groupe Bull 's GCOS , Stratus OpenVOS , Fujitsu (formerly Siemens) BS2000 , and Fujitsu- ICL VME mainframes are still available in Europe, and Fujitsu (formerly Amdahl) GS21 mainframes globally. NEC with ACOS and Hitachi with AP10000- VOS3 still maintain mainframe businesses in
5246-450: The leftmost 9 bits, 0 to 8, contain an instruction opcode . Many of the possible 512 codes are not defined in the base model machines and are reserved for expansion like the addition of a hardware floating point unit . Following the opcode in bits 9 to 12 is the number of a register which will be used for the instruction. The input/output instructions all start with bits 0 through 2 being set to 1 (decimal value 7), bits 3 through 9 containing
SECTION 60
#17328595922815332-682: The main Scheduler might come from one university, the Disk Service from another, and so on. The commercial timesharing services such as CompuServe , On-Line Systems, Inc. (OLS), and Rapidata maintained sophisticated inhouse systems programming groups so that they could modify the operating system as needed for their own businesses without being dependent on DEC or others. There are also strong user communities such as DECUS through which users can share software that they have developed. Mainframe computer A mainframe computer , informally called
5418-473: The main processor. The 8080 switches modes after the operating system boots and controls the console and remote diagnostic serial ports. Two models of tape drives were supported by the TM10 Magnetic Tape Control subsystem: A mix of up to eight of these could be supported, using seven-track or nine-track devices. The TU20 and TU30 each came in A (9-track) and B (7-track) versions, and all of
5504-477: The mainframe. IBM's quarterly and annual reports in the 2000s usually reported increasing mainframe revenues and capacity shipments. However, IBM's mainframe hardware business has not been immune to the recent overall downturn in the server hardware market or to model cycle effects. For example, in the 4th quarter of 2009, IBM's System z hardware revenues decreased by 27% year over year. But MIPS (millions of instructions per second) shipments increased 4% per year over
5590-483: The memory location, and replaces the left half of the memory location with Ones. Halfword instructions are also used for linked lists: HLRZ is the Lisp CAR operator; HRRZ is CDR. The conditional jump operations examine register contents and jump to a given location depending on the result of the comparison. The mnemonics for these instructions all start with JUMP, JUMPA meaning "jump always" and JUMP meaning "jump never" – as
5676-472: The mid-1990s, when CMOS mainframe designs replaced the older bipolar technology. IBM claimed that its newer mainframes reduced data center energy costs for power and cooling, and reduced physical space requirements compared to server farms . Modern mainframes can run multiple different instances of operating systems at the same time. This technique of virtual machines allows applications to run as if they were on physically distinct computers. In this role,
5762-433: The most secure, with vulnerabilities in the low single digits, as compared to thousands for Windows , UNIX , and Linux . Software upgrades usually require setting up the operating system or portions thereof, and are non disruptive only when using virtualizing facilities such as IBM z/OS and Parallel Sysplex , or Unisys XPCL, which support workload sharing so that one system can take over another's application while it
5848-431: The new Telum microprocessor . A supercomputer is a computer at the leading edge of data processing capability, with respect to calculation speed. Supercomputers are used for scientific and engineering problems ( high-performance computing ) which crunch numbers and data, while mainframes focus on transaction processing. The differences are: Mainframes and supercomputers cannot always be clearly distinguished; up until
5934-476: The next 12 bits reserved, and the remaining bits being an indirect bit, a 4-bit register code, and an 18-bit displacement, or a "global indirect word", with its uppermost bit clear, the next bit being an indirect bit, the next 4 bits being a register code, and the remaining 30 bits being a displacement. The process of calculating the effective address generates a 12-bit section number and an 18-bit offset within that segment. The original PDP-10 operating system
6020-400: The next instruction (which is often an unconditional jump) depending on the result of the comparison. A simple example is CAMN A,LOC which compares the contents of register A with the contents of location LOC and skips the next instruction if they are not equal. A more elaborate example is TLCE A,LOC (read "Test Left Complement, skip if Equal"), which using the contents of LOC as a mask, selects
6106-538: The original PDP-10 memory bus, with external memory modules. Module in this context meant a cabinet, dimensions roughly (WxHxD) 30 x 75 x 30 in. with a capacity of 32 to 256 kWords of magnetic-core memory . The processors used in the DECSYSTEM-20 (2040, 2050, 2060, 2065), commonly but incorrectly called "KL20", use internal memory, mounted in the same cabinet as the CPU . The 10xx models also have different packaging; they come in
6192-533: The original tall PDP-10 cabinets, rather than the short ones used later on for the DECSYSTEM-20. The differences between the 10xx and 20xx models were primarily which operating system they ran, either TOPS-10 or TOPS-20 . Apart from that, differences are more cosmetic than real; some 10xx systems have "20-style" internal memory and I/O, and some 20xx systems have "10-style" external memory and an I/O bus. In particular, all ARPAnet TOPS-20 systems had an I/O bus because
6278-433: The past two years. Alsop had himself photographed in 2000, symbolically eating his own words ("death to the mainframe"). In 2012, NASA powered down its last mainframe, an IBM System z9. However, IBM's successor to the z9, the z10 , led a New York Times reporter to state four years earlier that "mainframe technology—hardware, software and services—remains a large and lucrative business for I.B.M., and mainframes are still
6364-603: The presence of two CPU drawers in a rack simply meant that there were two separate systems. The mass storage drawers, in such a case, would be divided between the CPU drawers, with a minimum of one per a CPU drawer. There are two models of mass storage drawers. One model may contain one to four 5.25-inch full-height non-removable, one 5.25-inch full-height removable or non-removable and two 5.25-inch half-height removable devices. The other model may contain one to five 5.25-inch full-height non-removable, one 5.25-inch removable and two 5.25-inch half-height removable devices. In both models,
6450-628: The primary reasons for their longevity, since they are typically used in applications where downtime would be costly or catastrophic. The term reliability, availability and serviceability (RAS) is a defining characteristic of mainframe computers. Proper planning and implementation are required to realize these features. In addition, mainframes are more secure than other computer types: the NIST vulnerabilities database, US-CERT , rates traditional mainframes such as IBM Z (previously called z Systems, System z, and zSeries), Unisys Dorado, and Unisys Libra as among
6536-410: The processor itself, it avoids the need to repeatedly read the series of instructions from main memory and thus performs the loop much more rapidly. The final set of I/O instructions are used to write and read condition codes on the device, CONO and CONI. Additionally, CONSZ will perform a CONI, bitmask the retrieved data against the value in E, and then skip the next instruction if it is zero, used in
6622-410: The settings of the panel switches while writing lights up the status lamps. Device 4 is the "priority interrupt", which can be read using CONI to gain additional information about an interrupt that has occurred. In processors supporting extended addressing, the address space is divided into "sections". An 18-bit address is a "local address", containing an offset within a section, and a "global address"
6708-613: The size and throughput of databases. Batch processing, such as billing, became even more important (and larger) with the growth of e-business, and mainframes are particularly adept at large-scale batch computing. Another factor currently increasing mainframe use is the development of the Linux operating system, which arrived on IBM mainframe systems in 1999. Linux allows users to take advantage of open source software combined with mainframe hardware RAS . Rapid expansion and development in emerging markets , particularly People's Republic of China ,
6794-457: The tape based MicroVAX Diagnostic TK70 tape. Once the console transferred control of the computer to the MIPS processor the MicroVAX sat essentially unused until the next boot. Code name MIPSFAIR. A pedestal uniprocessor system based on the Q-Bus . It replaced the DECsystem 5400. The 5500 came with native SCSI support, as well as support for DSSI disk drives. Code name MIPSFAIR-2. The DECsystem 5500
6880-418: The ultimate effective address used by the instruction is not E, but the address stored in memory location E. When using indirection, the data in word E is interpreted in the same way as the layout of the instruction; bits 0 to 12 are ignored, and 13 through 35 form I, X and Y as above. Instruction execution begins by calculating E. It adds the contents of the given register X (if not 0) to the offset Y; then, if
6966-410: Was a rough consensus among industry analysts that the mainframe was a dying market as mainframe platforms were increasingly replaced by personal computer networks. InfoWorld ' s Stewart Alsop infamously predicted that the last mainframe would be unplugged in 1996; in 1993, he cited Cheryl Currid, a computer industry analyst as saying that the last mainframe "will stop working on December 31, 1999",
7052-569: Was another Eastern Bloc manufacturer, producing the ODRA , R-32 and R-34 mainframes. Shrinking demand and tough competition started a shakeout in the market in the early 1970s—RCA sold out to UNIVAC and GE sold its business to Honeywell; between 1986 and 1990 Honeywell was bought out by Bull ; UNIVAC became a division of Sperry , which later merged with Burroughs to form Unisys Corporation in 1986. In 1984 estimated sales of desktop computers ($ 11.6 billion) exceeded mainframe computers ($ 11.4 billion) for
7138-451: Was simply called "Monitor", but was later renamed TOPS-10 . Eventually the PDP-10 system itself was renamed the DECsystem-10. Early versions of Monitor and TOPS-10 formed the basis of Stanford's WAITS operating system and the CompuServe time-sharing system. Over time, some PDP-10 operators began running operating systems assembled from major components developed outside DEC. For example,
7224-597: Was slightly faster than the newer VAX-11/750 , although more limited in memory. A smaller, less expensive model, the KS10, was introduced in 1978, using TTL and Am2901 bit-slice components and including the PDP-11 Unibus to connect peripherals. The KS10 was marketed as the DECSYSTEM-2020, part of the DECSYSTEM-20 range; it was DEC's entry in the distributed processing arena, and it was introduced as "the world's lowest cost mainframe computer system." The KA10 has
7310-506: Was the DEC 3000 Model 800S AXP packaged in a similar rack-mountable enclosure. The DECstation system module is repackaged in a CPU drawer, which is mounted in a rack with a mounting kit which permits the drawer to be slid in and out. The CPU module also contained an integrated TURBOchannel Extender, the power supply and a blower, which cooled the system. However, as the system module that these systems use does not feature multiprocessing capabilities,
7396-534: Was the top-of-the-line Uni-processor KA machine at the time when the PA1050 software package was introduced. Two other KA10 models were the uniprocessor 10/40, and the dual-processor 10/55. The KI10 introduced support for paged memory management, and also support a larger physical address space of 4 megawords . KI10 models include 1060, 1070 and 1077, the latter incorporating two CPUs. The original KL10 PDP-10 (also marketed as DECsystem-10) models (1080, 1088, etc.) use
#280719