The STEbus (also called the IEEE-1000 bus ) is a non-proprietary, processor-independent, computer bus with 8 data lines and 20 address lines. It was popular for industrial control systems in the late 1980s and early 1990s before the ubiquitous IBM PC dominated this market. STE stands for ST andard E urocard.
119-488: Although no longer competitive in its original market, it is valid choice for hobbyists wishing to make 'home brew' computer systems. The Z80 and probably the CMOS 65C02 are possible processors to use. The standardized bus allows hobbyists to interface to each other's designs. In the early 1980s, there were many proprietary bus systems, each with its own strengths and weaknesses. Most had grown in an ad-hoc manner, typically around
238-936: A Board Support Package is usually provided by the manufacturer for the supported operating system(s). When printing "PC/104" or its variants, it is common for the forward slash or dashes to be omitted. PC/104 may be abbreviated as PC104, PCI-104 abbreviated as PCI104, etc. Additionally, it is common for PC/104- Plus to be abbreviated with a plus sign (e.g. PC104+). Such abbreviations are not officially recognized in any PC/104 Consortium specifications or literature, however they have been in use for some time. PC/104 systems often require small, non-volatile storage, such as that afforded by compact flash and solid state disk (SSD) devices. These are often more popular than mechanical (rotating) hard drives. Compared to rotating disks, flash-based storage devices have limited lifetimes in terms of write cycles, but they are faster and draw less power. Additionally, their compactness and physical durability
357-593: A MOS Technology 8502 . Zilog was later producing a low-power Z80 suitable for the growing laptop computer market of the early 1980s. Intel produced a CMOS 8085 (80C85) used in battery-powered portable computers, such as the Kyocera -designed laptop from April 1983, also sold by Tandy (as TRS-80 Model 100 ), Olivetti, and NEC. In following years, however, CMOS versions of the Z80 (from both Zilog and Japanese manufacturers) would dominate this market as well, in products such as
476-468: A rack-mounting system robust enough for industrial use, with easily interchangeable boards and processor independence. Researchers describe STEbus systems as rugged, adaptable, and cost effective. The STEbus market began to decline as the IBM PC made progress into industrial control systems. Customers opted for PC-based products as the software base was larger and cheaper. More programmers were familiar with
595-654: A 16-bit address register HL. In the 8080, this pairing was added to the BC and DE pairs as well, while HL was generalized to allow use as a 16-bit accumulator, not just an address register. The 8080 also introduced immediate 16-bit data for BC, DE, HL, and SP loads. Furthermore, direct 16-bit copying between HL and memory was now possible, using a direct address. The Z80 orthogonalized this further by making all 16-bit register pairs, including IX and IY, more general purpose, as well as allowing 16-bit copying directly to and from memory for all of these pairs. The 16-bit IX and IY registers in
714-441: A CPU board, power supply board, and one or more peripheral boards. The maximum number of boards supported by a PC/104 stack will depend on which buses are used by the peripheral boards. Regardless of the buses used, the maximum number of boards of a PC/104 stack may be limited due to size, weight, and power restrictions for the target application. When stacking PC/104 boards together, mechanical interference between adjacent boards
833-481: A PC/104 system (Serial Ports, USB, Ethernet, VGA, etc.) are typically supported via the native drivers built into the operating system. Certain peripheral boards, such as data acquisition may require special drivers from the board manufacturer. From a software development perspective, there is little difference between compiling software for a desktop PC or compiling for an x86 PC/104 stack. Software can be developed using standard x86 compilers (e.g. Visual Studio if
952-490: A PCI-104 expansion bus. The PC/104 Consortium specifications define a variety a computer buses, all of which derive from the ISA, PCI, and PCI Express buses found in a desktop PC. The original PC/104 bus derives from the ISA bus . It includes all the signals found on the ISA bus, with additional ground pins added to ensure bus integrity. Signal timing and voltage levels are identical to
1071-571: A PCI/104-Express peripheral module will communicate on the PCIe bus only; the PCI connector is simply a pass-through connector for stackability. A PC/104-Express peripheral module may not be used with a PCI-104 or PC/104- Plus CPU board (unless an ISA bridge device is used). PCI/104-Express incorporates link shifting, which eliminates the need for the PCI slot selection switches/jumpers found on PCI-104 and PC/104- Plus peripherals. Some peripheral boards re-populate
1190-445: A battery on board, often with a link to allow them to supply or accept power from VSTBY. Hence you can end up with more batteries in your system than you need, and you must then take care that no more than one battery is driving VSTBY. D0...7: Data bus. This is only 8-bits wide, but most I/O or memory-mapped peripherals are byte-oriented. A0...19: Address bus. This allows up to 1 MB of memory to be addressed. Current technology
1309-487: A byte and two T-states for each occurrence. This naturally makes the index register unavailable for any other use, or else the need to constantly reload it would negate its efficiency. PC/104 PC/104 (or PC104 ) is a family of embedded computer standards which define both form factors and computer buses by the PC/104 Consortium . Its name derives from the 104 pins on the interboard connector ( ISA ) in
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#17328520908351428-405: A copyright on their assembly mnemonics, a new assembly syntax had to be developed for the Z80. This time a more systematic approach was used: These principles made it straightforward to find names and forms for all new Z80 instructions, as well as orthogonalizations of old ones, such as LD BC,1234 . Apart from naming differences, and despite a certain discrepancy in basic register structure,
1547-473: A day later, Faggin and Ungermann were kicking around ideas based on "integrated logic" when Ungermann said "how about Zilog?" Faggin immediately agreed, stating they could say it was the "last word in integrated logic". When they met the next day and both immediately recalled it, the company had its name. The first samples were returned from Mostek on March 9, 1976. By the end of the month, they had also completed an assembler -based development system . Some of
1666-500: A high-level design, adding several concepts of his own. In particular, he used his experience on NEC minicomputers to add the concept of two sets of processor registers so they could quickly respond to interrupts . Ungerman began the development of a series of related controllers and peripheral chips that would complement the design. Through this period, Shima developed a legendary reputation for being able to convert logic concepts into physical design in realtime; while discussing
1785-462: A low-cost product like this would not be able to compete with a design from a company with its own production lines, like Intel. They then began considering a more complex microprocessor instead, initially known as the Super 80, with the main feature being its use of a +5 V bus instead of the more common −5, +5 and 12 V used by designs like the 8080. The new design was intended to be compatible with
1904-458: A method using only the 8080-model registers. The Z80 also introduced a new signed overflow flag and complemented the fairly simple 16-bit arithmetics of the 8080 with dedicated instructions for signed 16-bit arithmetics. The 8080-compatible registers AF, BC, DE, HL are duplicated as a separate register file in the Z80, where the processor can quickly (four t-states, the least possible execution time for any Z80 instruction) switch from one bank to
2023-529: A more rugged mounting than slot boards found in desktop PCs. The compact board size further contributes to the ruggedness of the form factor by reducing the possibility of PCB flexing under shock and vibration. A typical PC/104 system (commonly referred to as a "stack") will include a CPU board , power supply board, and one or more peripheral boards, such as a data acquisition module, GPS receiver, or Wireless LAN controller. A wide array of peripheral boards are available from various vendors. Users may design
2142-664: A particular microprocessor. The S-100 bus is based on Intel 8080 signals, the STD Bus around Z80 signals, the SS-50 bus around the Motorola 6800 , and the G64 bus around 6809 signals. This made it harder to interface other processors. Upgrading to a more powerful processor would subtly change the timings, and timing restraints were not always tightly specified. Nor were electrical parameters and physical dimensions. They usually used edge-connectors for
2261-455: A proposed feature, he would often interrupt and state how much room that would take on the chip and veto its addition if it was too large. The first pass at the design was complete by April 1975. Shima had completed a logic layout by the beginning of May. A second version of the logic design was issued on August 7 and the bus details by September 16. Tape-out was completed in November and converting
2380-687: A range of price and performance. These boards included the Intel 8031 , 8085 , 8088 , 80188 ; the National Semiconductor 32008 and 32016 ; the Motorola 6809 , 68000 , and 68008 ; The Zilog Z80 and Z280 ; the Hitachi HD64180 ; and the Inmos Transputer . The STEbus is designed for 8-bit microprocessors. Processors that normally use a wider data bus ( 16-bit , etc.) can use the STEbus if
2499-422: A regular encoding (common with the 8080) is that each of the 8-bit registers can be loaded from themselves (e.g. LD A,A ). This is effectively a NOP . New block transfer instructions can move up to 64 kilobytes from memory to memory or between memory and I/O peripheral ports. Block instructions LDIR and LDDR ( l oa d , i ncrement/ d ecrement, r epeat) use HL to point to the source address, DE to
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#17328520908352618-501: A relative address ( JR instead of JP ) using a signed 8-bit displacement. Only the zero and carry flags can be tested for these new two-byte JR instructions. (All 8080 jumps and calls, conditional or not, are three-byte instructions.) A two-byte instruction specialized for program looping is also new to the Z80: DJNZ ( d ecrement j ump if n on- z ero) takes a signed 8-bit displacement as an immediate operand. The B register
2737-456: A stack that incorporates boards from multiple vendors. The overall height, weight, and power consumption of the stack can vary depending on the number of boards that are used. PC/104 is sometimes referred to as a "stackable PC", as most of the architecture derives from the desktop PC. The majority of PC/104 CPU boards are x86 compatible and include standard PC interfaces such as Serial Ports , USB , Ethernet , and VGA . A x86 PC/104 system
2856-518: A system not using interrupts) it can be used as simply another 8-bit data register. The instructions LD A,R and LD A,I affect the Z80 flags register, unlike all the other LD (load) instructions. The Sign (bit 7) and Zero (bit 6) flags are set according to the data loaded from the Refresh or Interrupt source registers. For both instructions, the Parity/Overflow flag (bit 2) is set according to
2975-544: A total of $ 10 million for the entire industry being spent in all of 1975 (equivalent to $ 57 million in 2023). Someone from Exxon contacted the still-unnamed company, and arranged a meeting that eventually led to them providing an initial $ 500,000 funding in June 1975 (equivalent to $ 2.8 million in 2023). With funding being discussed, and a design to be built, Shima joined in February 1975. Shima immediately set about producing
3094-407: A unique address. CM0...2: Command Modifiers. These indicate the nature of the data transfer cycle. A simple processor board can drive CM2 high for all bus access, drive CM1 from a memory/not_IO signal, and CM0 from a read/not_write signal. CM2 low state is used only during "attention request" phases (for interrupts and/or DMA cycles) for Explicit Response mode. When Implicit Response mode is used,
3213-428: A variable base address (as in recursive stack frames ) and can also reduce code size by removing the need for multiple short instructions using non-indexed registers. However, although they may save speed in some contexts when compared to long/complex "equivalent" sequences of simpler operations, they incur a lot of additional CPU time (e.g., 19 T-states to access one indexed memory location vs. as little as 11 to access
3332-521: A week in order to meet the tight schedule given by the financial investors. The Z80 offered many improvements over the 8080: The Z80 took over from the 8080 and its offspring, the 8085 , in the processor market and became one of the most popular and widely used 8-bit CPUs. Some organizations such as British Telecom remained loyal to the 8085 for embedded applications, owing to their familiarity with it and to its on-chip serial interface and interrupt architecture. Likewise, Zenith Data Systems paired
3451-418: Is a concern. The mechanical interference issues listed above can often be addressed with a Bus Spacer, which allows additional room between the boards. However, Bus Spacers increase overall stack height, and may not be suitable for space-constrained applications. It may also be possible to re-arrange the boards in the stack to remove the interference. Another option is to modify the offending boards to remove
3570-550: Is decremented, and if the result is nonzero, then program execution jumps relative to PC; the flags remain unaltered. To perform an equivalent loop on an 8080 requires separate DEC and conditional jump (to a two-byte absolute address) instructions (totalling four bytes), and the DEC alters the flag register. The index register (IX/IY, often abbreviated XY) instructions can be useful for accessing data organised in fixed heterogenous structures (such as records ) or at fixed offsets relative
3689-510: Is in context unless carefully commented. Thus it is advisable that exchange instructions be used directly and in short discrete code segments. The Zilog Z280 instruction set includes JAF and JAR instructions which jump to a destination address if the alternate registers are in context (thus officially recognizing this programming complication). As on the 8080, 8-bit registers are typically paired to provide 16-bit versions. The 8080 compatible registers are: The new registers introduced with
STEbus - Misplaced Pages Continue
3808-472: Is incompatible with PC/104 peripheral module. However, PCI-104 and PC/104- Plus are compatible, since they both utilize the PCI bus. Most PC/104- Plus boards can be manufactured as PCI-104 by simply not populating the PC/104 connector. PCI-104 utilizes the same PCI Slot Number selection scheme as PC/104- Plus . Each device must be assigned to a unique slot number. The PCI/104-Express specification incorporates
3927-402: Is incompatible with Type 2 peripherals, or vice versa. The specification requires the system to remain in reset and not boot in the case of a Type mismatch (no physical damage will occur). Universal peripheral boards may be used with either Type 1 or Type 2 pinouts. Because the PCIe bus connector is surface-mount, not through-hole, it is also possible for a board to use different bus pinouts on
4046-503: Is necessary to specify the PCI Slot Number of a peripheral board when it is installed. This is commonly set by a rotary switch , DIP switch , or jumpers on the peripheral board. Each PCI peripheral board in the system must have the PCI Slot Number set to a unique value. Failure to do so may cause erratic system behavior. The peripheral closest to the CPU should be set for the first slot,
4165-587: Is often referred to as the "alternate register set" (by some, the "primed" register file since the apostrophe character is used to denote them in assembler source code and the Zilog documentation). This emphasizes that only one set is addressable at any time. However, the 8-bit accumulator A with its flag register F is bifurcated from the "general purpose" register pairs HL, DE and BC. This is accomplished with two separate instructions used to swap their accessibilities: EX AF,AF' exchanges only register pair AF with AF', while
4284-581: Is only one Master, the System Controller is not needed, and SYSCLK can be generated by the Master board Z80 The Zilog Z80 is an 8-bit microprocessor designed by Zilog that played an important role in the evolution of early computing. Launched in 1976 and software-compatible with the Intel 8080 , it offered a compelling alternative due to its better integration and increased performance. As well as
4403-464: Is rather like a VMEbus simplified for 8-bit processors. The bus signals are sufficiently generic so that they are easy for 8-bit processors to interface with. The board size was usually a single-height Eurocard (100 mm x 160 mm) but allowed for double-height boards (233 x 160 mm) as well. The latter positioned the bus connector so that it could neatly merge into VME-bus systems. IEEE Working Group P1000 initially considered simply repinning
4522-451: Is recommended for analogue circuitry. VSTBY: Standby voltage. Optional. This line is specified as 5V (+0 to +5%), at up to 1A. However, some boards have used this line for carrying a battery backup voltage to boards that supply or consume it. A 3.6V NiCad battery is a common source. The STEbus spec is not rigid about where this should be sourced from. In practice, this means that most boards requiring backup power tend to play safe and have
4641-502: Is somewhat smaller than a desktop PC motherboard at 3.550 × 3.775 inches (90 × 96 mm). Unlike other popular computer form factors such as ATX , which rely on a motherboard or backplane , PC/104 boards are stacked on top of each other like building blocks. The PC/104 specification defines four mounting holes at the corners of each module, which allow the boards to be fastened to each other using standoffs . The stackable bus connectors and use of standoffs provides
4760-488: Is such that processor requiring large amounts of memory have this on the processor board, so this is not a great limitation. I/O space is limited to 4K, to simplify I/O address decoding to a practical level. A single 74LS688 on each slave board can decode A11...A4 to locate I/O slave boards at any I/O address with 16-byte alignment. Typically 8 small jumpers or a single unit of 8 DIP switches or two binary-coded hexadecimal rotary switches are used to give each I/O slave board
4879-551: Is the ZX81 , which lets it keep track of character positions on the TV screen by triggering an interrupt at wrap around (by connecting INT to A6). The interrupt vector register , I , is used for the Z80 specific mode 2 interrupts (selected by the IM 2 instruction). It supplies the high byte of the base address for a 128-entry table of service routine addresses which are selected via an index sent to
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4998-449: Is the primary signal in data transfer cycles. DATACK*: Data Acknowledge. A slave will assert this signal when to acknowledge the safe completion of a data transfer via the STEbus. This allows STEbus systems to use plug-in cards with a wide variety of speeds, an improvement on earlier bus systems that require everything to run at the speed of the slowest device. TFRERR*: Transfer Error. A slave will assert this signal when acknowledging
5117-414: Is used as the byte counter. The Z80 can input and output any register to an I/O port using register C to designate the port. (The 8080 only performs I/O through the accumulator A, using a direct port address specified in the instruction; a self-modifying code technique is required to use a variable 8080 port address.) The last group of block instructions perform a CP compare operation between
5236-498: Is usually capable of standard PC operating system such as DOS, Windows, or Linux. However, it is also quite common to use a real-time operating system , such as VxWorks . The PC/104 bus and form factor was originally devised by Ampro in 1987 (led by CTO Rick Lehrbaum), and later standardized by the PC/104 Consortium in 1992. An IEEE standard corresponding to PC/104 was drafted as IEEE P996.1, but never ratified. In 1997,
5355-561: The EXX instruction exchanges the three general purpose register pairs HL, DE and BC with their alternates HL', DE' and BC'. Thus the accumulator A can interact independently with any of the general purpose 8-bit registers in the alternate (or primed) register file, or, if HL' contains a pointer to memory, some byte there (DE' and BC' can also transfer 8-bit data between memory and accumulator A). This can become confusing for programmers because after executing EX AF,AF' or EXX what were previously
5474-718: The Amstrad NC100 , Cambridge Z88 and Tandy's own WP-2. Perhaps a key to the initial success of the Z80 was the built-in DRAM refresh, at least in markets such as CP/M and other office and home computers. (Most Z80 embedded systems use static RAM that do not need refresh.) It may also have been its minimalistic two-level interrupt system, or conversely, its general multi-level daisy-chain interrupt system useful in servicing multiple Z80 IO chips. These features allowed systems to be built with less support hardware and simpler circuit board layouts. However, others claim that its popularity
5593-577: The CP/M operating system and Intel's PL/M compiler for 8080 (as well as its generated code), would run unmodified on the new Z80 CPU. Masatoshi Shima designed most of the microarchitecture as well as the gate and transistor levels of the Z80 CPU, assisted by a small number of engineers and layout people. CEO Federico Faggin was actually heavily involved in the chip layout work, together with two dedicated layout people. According to Faggin, he worked 80 hours
5712-595: The PCI Express bus (PCIe) in addition to the previous-generation PCI bus. The specification defines a 156-pin surface mount connector for the PCI Express signals. The new connector occupies the same board location as the legacy PC/104 ISA connector. In addition to PCI Express, the specifications also defines pins on the connector for additional modern computer buses, such as USB , SATA , and LPC . The PCI/104-Express specification currently defines two possible pinouts for
5831-535: The PCI bus , in addition to the ISA bus of the PC/104 standard. The name is derived from its origin: a PC/104- Plus module has a PC/104 connector (ISA) plus a PCI connector. The standard defines a 120-pin connector for the PCI bus, located on the opposite side of the board from the PC/104 connector. PC/104- Plus CPU boards provide active communication on both buses, and are capable of communicating with both ISA and PCI peripheral cards. On PC/104- Plus peripheral modules,
5950-580: The STD Bus , replacing its card edge connector with the DIN41612 connector. But they decided to create a completely new high-performance 8-bit bus. They decided to make a bus more like the VMEbus and Futurebus . The STEbus was designed to be manufacturer independent, processor independent, and have multimaster capability. The STEbus was very successful in its day. It was given the official standard IEEE 1000-1987. Many processors were available on STEbus cards, across
6069-473: The "104" name to distinguish the form factor from the legacy PC/104 bus. EBX (Embedded Board eXpandable) is a single board computer form factor, 5.75 × 8 in (146 × 203 mm). The EBX form factor applies to the CPU board , but supports PC/104 form factor peripheral boards for expansion. The original EBX specifications allowed for the PC/104, PC/104- Plus , and PCI-104 buses. EBX Express adds
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#17328520908356188-420: The 16-bit version. Since PC/104 is based on the ISA bus, it is often necessary to set the base address , IRQ , and DMA channel when installing a peripheral board. This is usually accomplished via the use of jumpers or DIP switches on the peripheral board. Failure to configure the peripheral correctly can cause a resource conflict and lead to erratic behavior. The PC/104- Plus standard adds support for
6307-449: The 8080's seven registers and flags register, the Z80 had an alternate register set that duplicated them, two 16-bit index registers and additional instructions including bit manipulation and block copy/search. Initially intended for use in embedded systems like the 8080, the Z80's combination of compatibility, affordability, and superior performance propelled it to widespread adoption in video game systems and home computers during
6426-406: The 8080); the four remaining codes are used extensively as opcode prefixes : CB and ED enable extra instructions, and DD or FD select IX+d or IY+d respectively (in some cases without displacement d) in place of HL. This scheme gives the Z80 a large number of permutations of instructions and registers; Zilog categorizes these into 158 different "instruction types", 78 of which are the same as those of
6545-430: The 8080, as the Z80 sometimes indicates signed overflow where the 8080 would indicate parity, possibly causing the logic of some practical 8080 software to fail on the Z80. ) This new overflow flag is used for all new Z80-specific 16-bit operations ( ADC , SBC ) as well as for 8-bit arithmetic operations, while the 16-bit operations inherited from the 8080 ( ADD , INC , DEC ) do not affect it. Also, bit 1 of
6664-445: The 8080, but add many of the nice features of the Motorola 6800 , including index registers and improved interrupts . While still being set up, the industry newsletter Electronic News heard of them and published a story on the newly formed company. This attracted the attention of Exxon Enterprises, Exxon 's high-tech investment arm. At the time, in the midst of the recession, there was very little venture capital available, with
6783-645: The 8085 with the 16-bit Intel 8088 in its first MS-DOS computer, the Zenith Z-100 , despite having previous experience with its pioneering Z80-based Heathkit H89 and Zenith Z-89 products. However, other computers were made integrating the Z80 with other CPUs: the Radio Shack TRS-80 Model ;16 with a Motorola 68000 , the DEC Rainbow with an 8088, and the Commodore ;128 with
6902-464: The CPU during an interrupt acknowledge cycle; this index is simply the low byte part of the pointer to the tabulated indirect address pointing to the service routine. The pointer identifies a particular peripheral chip or peripheral function or event, where the chips are normally connected in a so-called daisy chain for priority resolution. Like the refresh register, this register has also sometimes been used creatively; in interrupt modes 0 and 1 (or in
7021-504: The DIN connectors in parallel. So a STEbus expansion card sees the same signals no matter which slot of the backplane it is plugged into. The SYSCLK must be driven by only one board in the system. As explained in the standard, this signal shall be generated by the System Controller. The System Controller is also in charge of the Bus Arbitration in case there are multiple masters. When there
7140-590: The Form Factors listed below, it is possible for a non-standard or proprietary form factor to incorporate one of the PC/104 Bus Structures for expandability. Note the term "PC/104" is often used interchangeably to refer to either the Bus Structure or Form Factor. This can be a source of confusion. For example, a product datasheet may refer to a board as "PC/104" due to its size and shape when it in fact has
7259-604: The I/O connector area. The extended PCB "wings" is not addressed in the specification, generally does not cause mechanical issues as long as the overall PCB + I/O connector overhang is within the maximum allowable dimensions of 4.550 × 4.393 inches (116 × 112 mm). The dimensions were originally defined in the PC/104 Specification, and as a result the form factor is still commonly referred to as "PC/104". The PCI/104-Express and PCIe/104 Specification introduced
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#17328520908357378-517: The ISA bus, with lower current requirements. The PC/104 specification defines two versions of the bus, 8-bit or 16-bit. The 8-bit version corresponds to the IBM XT and consists of 64 pins. The 16-bit version corresponds to the IBM AT and adds 40 additional pins, bringing the total to 104 (hence the name "PC/104"). The signals marked J1/P1 are found on both versions, while the signals of J2/P2 are found only on
7497-412: The Intel 8080 (allowing operation of all 8080 programs on a Z80). The Zilog documentation further groups instructions into the following categories (most from the 8080, others entirely new like the block and bit instructions, and others 8080 instructions with more versatile addressing modes, like the 16-bit loads, I/O, rotates/shifts and relative jumps): No explicit multiply instructions are available in
7616-566: The PC and did not have to learn new systems. Memory costs fell, so there was less reason to have bus-based memory expansion when one could have plenty on the processor board. So despite the disadvantages, manufacturers created industrial PC systems and eventually dropped other bus systems. As time went on, PC systems did away with the need for card cages and backplanes by moving to the PC/104 format where boards stack onto each other. While not as well-designed as
7735-488: The PC/104 Consortium define multiple of Bus Structures (ISA, PCI, PCI Express) and Form Factors (104, EBX, EPIC). Bus Structure defines the location and pinout of the bus connector(s). Form Factor refers to size and shape of the board. It is possible to find one of the PC/104 stackable expansion buses on a number of different form factors. While most commercially available products using the Bus Structures will comply with
7854-500: The PC/104 Consortium introduced a newer standard based on the PCI bus . A PCI Express -based standard was introduced in 2008. PC/104-related specifications are controlled by the PC/104 Consortium. There are currently 47 members of the Consortium. All specifications published by the Consortium are freely available. Membership in the Consortium is not required to design and manufacture a PC/104 board. The specifications released by
7973-433: The PC/104 connector is simply a passive connector for stackability; the module actively communicates on the PCI bus only. As a corollary, a PC/104- Plus peripheral module may not be used with a PC/104 CPU board. However, a PC/104- Plus CPU board may be used with a PC/104 peripheral module. Since PC/104- Plus is based on PCI, there is no need to set a Base Address, IRQ, or DMA channel on the peripheral boards. However, it
8092-503: The PC/104 system is running Windows). There is typically no need for specialized development tools, such as cross compilers , Board Support Packages , or JTAG debuggers . This is a significant departure from non-x86 embedded system platforms, which often require a development toolchain from the board manufacturer. Non-x86 PC/104 CPU boards based on ARM or PowerPC are also commercially available. However, such boards are not capable of running off-the-shelf PC software. In these cases,
8211-710: The PCI-104/Express and PCIe/104 buses. EPIC (Embedded Platform for Industrial Computing) is a single-board computer form factor which, like EBX, supports PC/104 peripheral boards but is smaller than EBX at 6.5 × 4.5 in (165 × 114 mm). It allows I/O connections to be implemented as either pin headers or PC-style ("real world") connectors. The standard provides specific I/O zones to implement functions such as Ethernet, serial ports, digital and analog I/O, video, wireless, and various application-specific interfaces. EPIC Express adds PCI Express expandability. In general, every PC/104 stack will contain
8330-432: The PCIe connector: CPU boards and peripherals may be designed as Type 1, Type 2, or Universal (which only uses the common subset of signals between the two types, PCIe x1 and/or USB 2.0). The Type 2 pinout was not introduced until Version 2.0 of the specification (released in 2011). PCI/104-Express products introduced prior to 2011 will be either Type 1 or Universal, but may not be explicitly labeled as such. A Type 1 bus
8449-459: The PCIe links, which allows the stack to have additional peripheral boards beyond the initial set of PCI Express links provided by CPU board. Link repopulation is not a requirement in the specification, and must be implemented on the peripheral board with a PCI Express packet switch. PCIe/104 is similar to the PCI/104-Express standard, but omits the legacy PCI bus to increase available space on
8568-463: The STEbus, PC/104 is good enough for many applications. The major manufacturers from its peak period now support STEbus mostly for goodwill with old customers who bought a lot of product from them. As of 2013, some manufacturers still support STEbus, G64, Multibus II, and other legacy bussed systems. The IEEE have withdrawn the standard, not because of any faults but because it is no longer active enough to update. 3U Eurocard - The most common size
8687-461: The Z80 and 8086 syntax are virtually isomorphic for a large portion of instructions. Only quite superficial similarities (such as the word MOV, or the letter X, for extended register) exist between the 8080 and 8086 assembly languages, although 8080 programs can be translated to 8086 assembly language by translator programs . The Z80 uses 252 out of the available 256 codes as single byte opcodes ("root instruction" most of which are inherited from
8806-567: The Z80 are fairly conventional, ultimately based on the register structure of the Datapoint 2200 . The Z80 was designed as an extension of the Intel 8080, created by the same engineers, which in turn was an extension of the 8008 . The 8008 was basically a PMOS implementation of the TTL-based CPU of the Datapoint 2200. The 2200 design allowed 8-bit registers H and L (High and Low) to be paired into
8925-469: The Z80 are primarily intended as base address-registers, where a particular instruction supplies a constant offset that is added to the previous values, but they are also usable as 16-bit accumulators, among other things. A limitation is that all operand references involving IX or IY require an extra instruction prefix byte, adding at least four clock cycles over the timing of an instruction using HL instead; this sometimes makes using IX or IY less efficient than
9044-424: The Z80 are: The refresh register , R , increments each time the CPU fetches an opcode (or an opcode prefix, which internally executes like a 1-byte instruction) and has no simple relationship with program execution. This has sometimes been used to generate pseudorandom numbers in games, and also in software protection schemes. It has also been employed as a "hardware" counter in some designs; an example of this
9163-491: The Z80 in April 2024 after nearly five decades of production. At Fairchild Semiconductor , and later at Intel , physicist and engineer Federico Faggin had been working on fundamental transistor and semiconductor manufacturing technology. He also developed the basic design methodology used for memories and microprocessors at Intel and led the work on the Intel 4004 , the Intel 8080 and several other ICs. Masatoshi Shima
9282-497: The Z80 support and peripheral ICs were under development at this point, and many of them were launched during the following year. Among them were the Z80 CTC (counter/timer), Z80 DMA (direct memory access), Z80 DART (dual asynchronous receiver–transmitter), Z80 SIO (synchronous communication controller), and Z80 PIO (parallel input/output). The Z80 was officially launched in July 1976. One of
9401-467: The Z80. However, this would likely be erroneous code on the 8080, as DAA was defined for addition only on that processor. The Z80 has six new LD instructions that can load the DE, BC, and SP register pairs from memory, and load memory from these three register pairs—unlike the 8080. As on the 8080, load instructions do not affect the flags (except for the special-purpose I and R register loads). A result of
9520-464: The alternate (primed) registers are now the main registers, and vice versa. The only way for the programmer to tell which set(s) are in context (while "playing computer" while scrutinizing the assembler source text, or worse, poring over code with a debugger) is to trace where each register swap is made at each point in the program. Obviously if many jump and calls are made within these code segments it can quickly become difficult to tell which register file
9639-423: The board (similar to the relationship between PC/104- Plus and PCI-104). The PCI Express connector location and pinout options the same as PCI/104-Express (both Type 1 and Type 2). Because the PCI bus connector is omitted, a PCIe/104 board is incompatible with PC/104- Plus and PCI-104 systems (unless a PCIe-to-PCI bridge device is used). The PC/104 Consortium's specifications cover three form factors which define
9758-570: The bus master polls the slave boards to find which one has triggered the Attention Request and reset the signal source. In that case, Vector-fetch is not used. ATNRQ0...7*: Attention Requests. These are reserved for boards to signal for processor attention, a term which covers Interrupts and Direct Memory Access (DMA). The wise choice of signal does not commit these lines to being specific types, such as maskable interrupts, non-maskable interrupts, or DMA. The number of Attention Requests reflects
9877-419: The bus, which were vulnerable to dirt and vibration. The VMEbus had provided a high-quality solution for high-performance 16-bit processors, using reliable DIN 41612 connectors and well-specified Eurocard board sizes and rack systems. However, these were too costly where an application only needed a modest 8-bit processor. In the mid 1980s, the STEbus standard addressed these issues by specifying what
9996-452: The byte at (HL) and the accumulator A. Register pair DE is not used. The repeating versions CPIR and CPDR only terminate if BC goes to zero or a match is found. HL is left pointing to the byte after ( CPIR ) or before ( CPDR ) the matching byte. If no match is found the Z ;flag is reset. There are non-repeating versions CPI and CPD . Unlike the 8080, the Z80 can jump to
10115-498: The current state of the IFF2 flip-flop. Although the Z80 is generally considered an eight-bit CPU, it has a four-bit ALU , so calculations are done in two steps. The first Intel 8008 assembly language was based on a very simple (but systematic) syntax inherited from the Datapoint 2200 design. This original syntax was later transformed into a new, somewhat more traditional, assembly language form for this same original 8008 chip. At about
10234-415: The design directly. Faggin thought this would mean they could never compete even if they set up their own lines, and the agreement fell through. He then turned to Mostek, who agreed to a term of exclusivity while Zilog got their lines set up, and were eventually given the second source agreement. After considering many names for the new company, and finding them so unmemorable they could not recall them even
10353-479: The design. Sometime later, Shima was told by an engineer within NEC that the traps had delayed their copying efforts by six months. The successful launch allowed Faggin and Ungermann to approach Exxon looking for funding to build their own fab. The company agreed, and Zilog built a production line very rapidly. This allowed them to capture about 60 to 70% of the total market for Z80 sales. With their own line running, Mostek
10472-566: The destination address, and BC as a byte counter. Bytes are copied from source to destination, the pointers are incremented or decremented, and the byte counter is decremented until BC reaches zero. Non-repeating versions LDI and LDD move a single byte and bump the pointers and byte counter, which if it becomes zero resets the P/V ;flag. Corresponding memory-to-I/O instructions INIR , INDR , OTIR , OTDR , INI , IND , OUTI and OUTD operate similarly, except that B, not BC,
10591-522: The direction of Les Vadasz, further diluting the microprocessor's place in the company. That year, the 1973–1975 recession reached a peak and Intel laid off a number of employees. All of this led to Faggin becoming restless, and he invited Ungermann out for drinks and asked if he would be interested in starting their own company. Ungermann immediately agreed, and as he had less to do at Intel, left in August or September, followed by Faggin, whose last day at Intel
10710-508: The erroneous completion of a data transfer via the STEbus. ADRSTB*: Address Strobe. This signal indicates the address bus is valid. Originally, this had some practical use in DRAM boards which could start strobing the address lines into DRAM chips before the data bus was ready. The STEbus spec was later firmed up to say that slaves were not allowed to start transfers until DATSTB* was ready, so ADRSTB* has become quite redundant. Nowadays, STEbus masters can simply generate DATSTB* and ADRSTB* from
10829-481: The first customers was a buyer who, unknown to Zilog, worked for NEC. At the time, the Japanese electronics companies were well known for taking US chip designs and producing them without a license. The Zilog team had worried about this, and Faggin had come up with the idea of adding transistors that would be subtly modified to operate differently than a visual inspection would suggest. Shima added six of these "traps" around
10948-506: The flags register (a spare bit on the 8080) is used as a flag N that indicates whether the last arithmetic instruction executed was a subtraction or addition. The Z80 version of the DAA instruction (decimal adjust accumulator for BCD arithmetic) checks the N ;flag and behaves accordingly, so a (hypothetical) subtraction followed later by DAA will yield a different result on an old 8080 than on
11067-498: The intended role of the STEbus, in real-time control systems. Eight lines can be priority encoded into three bits, and is a reasonably practical number of lines to handle. BUSRQ0...1* and BUSAK0...1*: Bus Requests and Bus Acknowledge. Optional. Used by multi-master systems. The number of Attention Requests reflects that the STEbus aims to be simple. Single-master systems are the norm, but these signals allow systems to have secondary bus masters if needed. DATSTB*: Data Strobe. This
11186-568: The interference (e.g. depopulate a connector), but this may require the vendor to supply a customized version of the board. In theory, PC/104 boards are interoperable. It is possible to assemble a system using boards from several different vendors, subject to the fundamental Bus Structure compatibility issues listed above. However, compatibility issues sometimes appear. The majority of PC/104 CPU boards are x86 compatible , and are capable of running commercially available off-the-shelf PC software without modification. The standard PC I/O interfaces of
11305-631: The introductory 2.5 MHz , via the well known 4 MHz (Z80A), up to 6 MHz (Z80B) and 8 MHz (Z80H). The NMOS version has been produced as a 10 MHz part since the late 1980s. CMOS versions were developed with specified upper frequency limits ranging from 4 MHz up to 20 MHz for the version sold today. The CMOS versions allowed low-power standby with internal state retained, having no lower frequency limit. The fully compatible derivatives HD64180 / Z180 and eZ80 are currently specified for up to 33 MHz and 50 MHz, respectively. The programming model and register set of
11424-646: The late 1970s and early 1980s, fueling the personal computing revolution. Products it was used in include the Osborne 1 , Radio Shack TRS-80 , ColecoVision , ZX Spectrum and the Pac-Man cabinet; in later years it remained used in portables, best known for use in the Game Boy and TI-83 series . The Z80 was the brainchild of Federico Faggin , a key figure behind the creation of the Intel 8080. After leaving Intel in 1974, Faggin co-founded Zilog with Ralph Ungermann . The Z80
11543-401: The next board should be set for the second slot, etc. The PCI-104 form factor includes the PCI connector, but not the PC/104 connector, in order to increase the available board real estate. Even though the PCI connector has 120 pins instead of 104, the established name was kept. The PCI connector location and pinout is identical to PC/104- Plus . Since the ISA bus is omitted, a PCI-104 board
11662-399: The original PC/104 specification and has been retained in subsequent revisions, despite changes to connectors. PC/104 is intended for specialized environments where a small, rugged computer system is required. The standard is modular, and allows consumers to stack together boards from a variety of COTS manufacturers to produce a customized embedded system. The original PC/104 form factor
11781-426: The original Z80 (being 1 clock slower than in the 8080/8085); nonetheless, they are about twice as fast as performing the same calculations using 8-bit operations, and equally important, they reduce register usage. It was not uncommon for programmers to "poke" different offset displacement bytes (which were typically calculated dynamically) into indexed instructions; this is an example of self-modifying code , which
11900-407: The original Z80, though registers A and HL can be multiplied by powers of two with ADD A,A and ADD HL,HL instructions (similarly IX and IY also). Shift instructions can also multiply or divide by powers of two. Different sizes and variants of additions, shifts, and rotates have somewhat differing effects on flags because most of the flag-changing properties of the 8080 were copied. However,
12019-483: The other; a feature useful for speeding up responses to single-level, high-priority interrupts. A similar feature was present in the 2200, but was never implemented at Intel. The dual register-set is very useful in the embedded role, as it improves interrupt handling performance, but found widespread use in the personal computer role as an additional set of general registers for complex code like floating-point arithmetic or home computer games. The duplicate register file
12138-418: The parity flag bit P of the 8080 (bit 2) is called P/V (parity/overflow) in the Z80 as it serves the additional purpose of a twos complement overflow indicator, a feature lacking in the 8080. Arithmetic instructions on the Z80 set it to indicate overflow rather than parity, while bitwise instructions still use it as a parity flag. (This introduces a subtle incompatibility of the Z80 with code written for
12257-648: The processor can handle data in byte-wide chunks, giving the slave as long as it needs to respond. The STEbus supported processors from the popular Z80, the 6809, to the 68020 . The only popular micro notably absent was the 6502, because it did not naturally support wait-states while writing. The CMOS 65C02 did not have this shortcoming, but this was rarer and more expensive than the NMOS 6502 and Z80. The 6809 used cycle stretching. Peripheral boards included prototyping boards, disc controllers, video cards, serial I/O, analogue and digital I/O. The STEbus achieved its goal of providing
12376-562: The same logic signal. Slaves simply note when DATSTB* is valid (since the bus definition insists that the address will also be valid at the same time as the data). ADRSTB* also allows a bus master to retain ownership of the bus during indivisible read-modify-write cycles, by remaining active during two DATSTB* pulses. The sequence matches that of the 68008's bus. Other CPUs may require additional logic to create read-modify-write cycles. SYSCLK: System Clock. Fixed at 16 MHz. 50% duty cycle. SYSRST*: System Reset. The backplane connects all
12495-535: The same memory using HL and INC to point to the next). Thus, for simple or linear accesses of data, use of IX and IY tend to be slower and occupy more memory. Still, they may be useful in cases where the "main" registers are all occupied, by removing the need to save/restore registers. Their officially undocumented 8-bit halves (see below) can be especially useful in this context, for they incur less slowdown than their 16-bit parents. Similarly, instructions for 16-bit additions are not particularly fast (11 clocks) in
12614-517: The same time, the new assembly language was also extended to accommodate the additional addressing modes in the more advanced Intel 8080 chip (the 8008 and 8080 shared a language subset without being binary compatible ; however, the 8008 was binary compatible with the Datapoint 2200). In this process, the mnemonic L , for LOAD , was replaced by various abbreviations of the words LOAD , STORE and MOVE , intermixed with other symbolic letters. The mnemonic letter M , for memory (referenced by HL),
12733-476: The size and shape of the board. Each form factor may utilize one of the Bus Structures listed above. The 104 Form Factor is defined to be 3.550 × 3.775 inches (90 × 96 mm), with mounting holes at all four corners of the board. The specifications also allow for a 0.5 inches (13 mm) area beyond the edge of the PCB for I/O connectors. Some PC/104 products have oversized PCBs which extended into
12852-438: The tape into a production mask required two more months. Faggin had already started looking for a production partner. By this time, Synertek and Mostek had both set up the depletion-mode production lines that could be used to produce the design. Having talked to Synertek previously, Faggin approached them first. However, the president of Synertek demanded that the company be given a second source license, allowing them to sell
12971-526: The top side of the board vs the bottom side. For example, a CPU board may have a Type 1 bottom PCIe connector and a Type 2 top PCIe connector. Such a CPU board would be compatible with Type 1 and/or Universal peripherals on the bottom, and compatible with Type 2 and/or Universal peripherals on the top. Similar to PC/104- Plus , a PCI/104-Express CPU boards will provide active communication on both PCI and PCIe buses. A PC/104-Express CPU board may be used with PCI-104 and PC/104- Plus peripheral modules. However,
13090-409: The value should be used as a memory address (as mentioned below), while the 8086 syntax uses brackets instead of ordinary parentheses for this purpose. Both Z80 and 8086 use the + sign to indicate that a constant is added to a base register to form an address. Note that the 8086 is not a complete superset of the Z80. BX is the only 8086 register pair that can be used as a pointer. Because Intel claimed
13209-418: The world market since large companies like NEC , Toshiba , Sharp , and Hitachi started to manufacture the device (or their own Z80-compatible clones or designs). The Z80 continued to be used in embedded systems for decades after its introduction, with ongoing advancements. The latest addition to the Z80 family is the eZ80 , which was offered alongside successor chips. Zilog announced the discontinuation of
13328-407: Was Halloween 1974. When Shima heard, he asked to come to the new company as well, but having no actual product design or money, they told him to wait. The newly formed and unnamed company initially began designing a single-chip microcontroller called the 2001. They met with Synertek to discuss fabrication on their lines, and when Faggin began to understand the costs involved it became clear that
13447-454: Was due to the duplicated registers that allowed fast context switches or more efficient processing of things like floating-point math compared to 8-bit CPUs with fewer registers. (The Z80 can keep several such numbers internally, using HL'HL, DE'DE and BC'BC as 32-bits registers, avoiding having to access them from slower RAM during computation.) For the original NMOS design, the specified upper clock-frequency limit increased successively from
13566-456: Was given the go-ahead to start sales of their own versions, the MK3880, which provided a second-source for customers which Intel lacked. At the time, a second-source was considered extremely important as a start-up like Zilog might go out of business and leave potential customers stranded. Faggin designed the instruction set to be binary compatible with the 8080 so that most 8080 code, notably
13685-546: Was lifted out from within the instruction mnemonic to become a syntactically freestanding operand , while registers and combinations of registers became very inconsistently denoted; either by abbreviated operands (MVI D, LXI H and so on), within the instruction mnemonic itself (LDA, LHLD and so on), or both at the same time (LDAX B, STAX D and so on). Illustration of four syntaxes, using samples of equivalent, or (for 8086) very similar, load and store instructions. The Z80 syntax uses parentheses around an expression to indicate that
13804-531: Was regular practice on nearly all early 8-bit processors with non- pipelined execution units. The index registers have a parallel instruction to JP (HL) , which is JP (XY) . This is often seen in stack-oriented languages like Forth , which at the end of every Forth word (atomic subroutines comprising the language) must jump unconditionally back to their thread interpreter routines. Typically this jump instruction appears many hundreds of times in an application, and using JP (XY) rather than JP THREAD saves
13923-459: Was released in July 1976. With the revenue from the Z80, the company built its own chip factories . Zilog licensed the Z80 to the US-based Synertek and Mostek , which had helped them with initial production, as well as to a European second-source manufacturer SGS . The design was also copied by several Japanese, Eastern European and Soviet manufacturers. This won the Z80 acceptance in
14042-769: Was the 100 x 160 mm Eurocard. 6U Eurocard - Rare, sometimes used in VMEbus hybrid boards DIN 41612 , rows a and c, 0.1" pitch. VME/STE hybrid boards have the STEbus and VMEbus sharing the VME P2 connector, VME signals on row b. For this reason, STEbus boards may not use row b for any purpose. Active low signals indicated by asterisk. GND: Ground reference voltage +5V: Powers most logic. +12V and -12V: Primarily useful for RS232 buffer power. The +12V has been used for programming voltage generators. Both can be used in analogue circuitry, but note that these are primarily power rails for digital circuitry and as such they often have digital noise. Some decoupling or local regulation
14161-430: Was the principal logic and transistor-level designer of the 4004 and the 8080 under Faggin's supervision, while Ralph Ungermann was in charge of custom integrated circuit design. In early 1974, Intel viewed their microprocessors not so much as products to be sold on their own but as a way to sell more of their main products, static RAM and ROM . A reorganization placed many of the formerly independent sections under
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