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54-581: It was one of the first computers to calculate in bit-parallel (rather than bit-serial ), and was the first to use magnetic-core memory . Its development led directly to the Whirlwind II design used as the basis for the United States Air Force SAGE air defense system, and indirectly to almost all business computers and minicomputers in the 1960s, particularly because of the mantra "short word length, speed, people." During World War II ,

108-550: A control store driven by a master clock. Each step of the clock selected one or more signal lines in a diode matrix that enabled gates and other circuits on the machine. A special switch directed signals to different parts of the matrix to implement different instructions. In the early 1950s, Whirlwind I "would crash every 20 minutes on average." Whirlwind construction started in 1948, an effort that employed 175 people, including 70 engineers and technicians. The use of carry save multiplication appears to have been first introduced in

162-454: A SRAM writable control store, loaded on power-on through another CPU. WCS offers several advantages including the ease of patching the microprogram and, for certain hardware generations, faster access than ROMs could provide. User-programmable WCS allow the user to optimize the machine for specific purposes. However, it also had the disadvantage of making it harder to debug programs, and making it possible for malicious users to negatively affect

216-547: A considerably more realistic aerodynamics model that could be adapted to any type of plane. This was an important consideration at the time, when many new designs were being introduced into service. The Servomechanisms Lab in MIT building 32 conducted a short survey that concluded such a system was possible. The Navy's Office of Naval Research decided to fund development under Project Whirlwind (and its sister projects, Project Typhoon and Project Cyclone , with other institutions), and

270-415: A data storage medium, Forrester obtained a workbench in the corner of the lab, and got several samples of the material to experiment with. Then for several months he spent as much time in the lab as he did in the office managing the entire project. At the end of those months, he had invented the basics of magnetic-core memory and demonstrated that it was likely to be feasible. His demonstration consisted of

324-542: A demonstration of ENIAC in 1945. He then suggested that a digital computer would be the best solution. Such a machine would allow the accuracy of simulations to be improved with the addition of more code in the computer program , as opposed to adding parts to the machine. As long as the machine was fast enough, there was no theoretical limit to the complexity of the simulation. Until this point, all computers constructed were dedicated to single tasks, and run in batch mode . A series of inputs were set up in advance and fed into

378-543: A form of read-only memory. This tradition dates back to the program timing matrix on the MIT Whirlwind , first described in 1947. Modern VLSI processors instead use matrices of field-effect transistors to build the ROM and/or PLA structures used to control the processor as well as its internal sequencer in a microcoded implementation. IBM System/360 used a variety of techniques: CCROS (Card Capacitor Read-Only Storage) on

432-414: A long tube filled with mercury , a mechanical transducer on one end, and a microphone on the other end, much like a spring reverb unit later used in audio processing. Pulses were sent into the mercury delay line at one end, and took a certain amount of time to reach the other end. They were detected by the microphone, amplified, reshaped into the correct pulse shape, and sent back into the delay line. Thus,

486-408: A register. This is because the machine will work faster if the execution of the next microinstruction is delayed by one cycle. This register is known as a pipeline register. Very often the execution of the next microinstruction is dependent on the result of the current microinstruction, which will not be stable until the end of the current microcycle. It can be seen that either way, all of the outputs of

540-422: A small core plane of 32 cores, each three-eighths of an inch in diameter. Having demonstrated that the concept was practical, it needed only to be reduced to a workable design. In the fall of 1949, Forrester enlisted graduate student William N. Papian to test dozens of individual cores, to determine those with the best properties. Papian's work was bolstered when Forrester asked student Dudley Allen Buck to work on

594-927: A year, which was vastly higher than the development costs of most other computers of the era. After three years, the Navy had lost interest. However, during this time the Air Force had become interested in using computers to help the task of ground controlled interception , and the Whirlwind was the only machine suitable to the task. They took up development under Project Claude . Whirlwind weighed 20,000 pounds (10 short tons; 9.1 t) and occupied over 2,000 square feet (190 m). The original machine design called for 2048 (2K) words of 16 bits each of random-access storage. The only two available memory technologies in 1949 that could hold this much data were mercury delay lines and electrostatic storage . A mercury delay line consisted of

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648-433: Is a form of parallel computing based on increasing processor word size . Increasing the word size reduces the number of instructions the processor must execute in order to perform an operation on variables whose sizes are greater than the length of the word. (For example, consider a case where an 8-bit processor must add two 16-bit integers . The processor must first add the 8 lower-order bits from each integer, then add

702-464: Is the part of a CPU's control unit that stores the CPU's microprogram . It is usually accessed by a microsequencer . A control store implementation whose contents are unalterable is known as a Read Only Memory (ROM) or Read Only Storage (ROS); one whose contents are alterable is known as a Writable Control Store (WCS). Early control stores were implemented as a diode-array accessed via address decoders,

756-494: Is typically loaded on power-on through some other front-end CPU. Many more machines offer user-programmable writable control stores as an option (including the HP 2100 , DEC PDP-11/60 and Varian Data Machines V-70 series minicomputers ). The Mentec M11 and Mentec M1 store its microcode in SRAM chips, loaded on power-on through another CPU. The Data General Eclipse MV/8000 ("Eagle") has

810-723: The Computer History Museum , is on shown as part of the Historic Computer Science displays at the Gates Computer Science Building, Stanford . The building which housed Whirlwind was until recently home to MIT's campus-wide IT department, Information Services & Technology and in 1997–1998, it was restored to its original exterior design. 42°21′42″N 71°5′48″W  /  42.36167°N 71.09667°W  / 42.36167; -71.09667 Bit-level parallelism Bit-level parallelism

864-601: The Model 30 , TROS (Transformer Read-Only Storage) on the Model 40 , and BCROS (Balanced Capacitor Read-Only Storage) on Models 50 , 65 and 67 . Some computers are built using "writable microcode" — rather than storing the microcode in ROM or hard-wired logic, the microcode is stored in a RAM called a writable control store or WCS . Such a computer is sometimes called a Writable Instruction Set Computer or WISC . Many of these machines were experimental laboratory prototypes, such as

918-454: The U.S. Navy 's Naval Research Lab approached MIT about the possibility of creating a computer to drive a flight simulator for training bomber crews. They envisioned a fairly simple system in which the computer would continually update a simulated instrument panel based on control inputs from the pilots. Unlike older systems such as the Link Trainer , the system they envisioned would have

972-400: The 1970s until about 1986, advancements in computer architecture were done by increasing bit-level parallelism, as 4-bit microprocessors were replaced by 8-bit , then 16-bit , then 32-bit microprocessors. This trend generally came to an end with the introduction of 32-bit processors, which were a standard in general purpose computing for two decades. 64 bit architectures were introduced to

1026-404: The 7AD7 was chosen instead, but this also had too high a failure rate in service. An investigation into the cause of the failures found that silicon in the tungsten alloy of the heater filament was causing cathode poisoning ; deposits of barium orthosilicate forming on the cathode reduce or prevent its function of emitting electrons . The 7AK7 tube with a high-purity tungsten filament

1080-475: The 8 higher-order bits, requiring two instructions to complete a single operation. A 16-bit processor would be able to complete the operation with single instruction.) Originally, all electronic computers were serial (single-bit) computers. The first electronic computer that was not a serial computer —the first bit-parallel computer—was the 16-bit Whirlwind from 1951. From the advent of very-large-scale integration (VLSI) computer chip fabrication technology in

1134-718: The WCS to run microcode for emulator features and hardware diagnostics. Other commercial machines that use writable microcode include the Burroughs Small Systems (1970s and 1980s), the Xerox processors in their Lisp machines and Xerox Star workstations, the DEC VAX 8800 ("Nautilus") family, and the Symbolics L- and G-machines (1980s). Some DEC PDP-10 machines store their microcode in SRAM chips (about 80 bits wide x 2 Kwords), which

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1188-554: The WISC CPU/16 and the RTX 32P. The original System/360 models have read-only control store, but later System/360, System/370 and successor models load part or all of their microprograms from floppy disks or other DASD into a writable control store consisting of ultra-high speed random-access read–write memory . The System/370 architecture includes a facility called Initial-Microprogram Load ( IML or IMPL ) that can be invoked from

1242-551: The Whirlwind I computer in Cambridge, Massachusetts . The Whirlwind II design for a larger and faster machine (never completed) was the basis for the SAGE air defense system IBM AN/FSQ-7 Combat Direction Central . The Whirlwind used approximately 5,000 vacuum tubes. An effort was also started to convert the Whirlwind design to a transistorized form, led by Ken Olsen and known as the TX-0 . TX-0

1296-400: The Whirlwind computer in the late 1940s. In the third quarter of 1949, the computer was advanced enough to solve an equation and display its solution on an oscilloscope, and even for the first animated and interactive computer graphic game. Finally Whirlwind "successfully accomplished digital computation of interception courses" on April 20, 1951. The project's budget was approximately $ 1 million

1350-538: The Williams tube, but determined that the dynamic nature of the storage and the need for frequent refresh cycles was incompatible with the design goals for Whirlwind I. Instead, they settled on a design that was being developed at the MIT Radiation Laboratory . This was a dual-gun electron tube. One gun produced a sharply-focused beam to read or write individual bits. The other gun was a "flood gun" that sprayed

1404-514: The beam current it could be determined whether the spot was originally a zero or a one, and a new value could be stored by the beam. There were several forms of electrostatic memory tubes in existence in 1949. The best known today is the Williams tube , developed in England, but there were a number of others that had been developed independently by various research labs. The Whirlwind engineers considered

1458-454: The computer, which would work out the answers and print them. This was not appropriate for the Whirlwind system, which needed to operate continually on an ever-changing series of inputs. Speed became a major issue: whereas with other systems it simply meant waiting longer for the printout, with Whirlwind it meant seriously limiting the amount of complexity the simulation could include. By 1947, Forrester and collaborator Robert Everett completed

1512-428: The console, as part of Power On Reset ( POR ) or from another processor in a tightly coupled multiprocessor complex. This permitted IBM to easily repair microprogramming defects in the field. Even when the majority of the control store is stored in ROM, computer vendors would often sell writable control store as an option, allowing the customers to customize the machine's microprogram. Other vendors, e.g., IBM, use

1566-490: The design of a high-speed stored-program computer for this task. Most computers of the era operated in bit-serial mode , using single-bit arithmetic and feeding in large words, often 48 or 60 bits in size, one bit at a time. This was simply not fast enough for their purposes, so Whirlwind included sixteen such math units, operating on a complete 16-bit word every cycle in bit-parallel mode. Ignoring memory speed, Whirlwind ("20,000 single-address operations per second" in 1951)

1620-404: The entire chip to be replaced. Such fixes can be installed by Linux, FreeBSD , Microsoft Windows, or the motherboard BIOS. The control store usually has a register on its outputs. The outputs that go back into the sequencer to determine the next address have to go through some sort of register to prevent the creation of a race condition . In most designs all of the other bits also go through

1674-429: The entire screen with low-energy electrons. As a result of the design, this tube was more of a static RAM that did not require refresh cycles, unlike the dynamic RAM Williams tube. In the end the choice of this tube was unfortunate. The Williams tube was considerably better developed, and despite the need for refresh could easily hold 1024 bits per tube, and was quite reliable when operated correctly. The MIT tube

Whirlwind I - Misplaced Pages Continue

1728-430: The experimental Microwave Early Warning (MEW) radar at Hanscom Field using Jack Harrington's equipment and commercial phone lines, aircraft were tracked by Whirlwind I. The Cape Cod System subsequently demonstrated computerized air defence covering southern New England . Signals from three long range (AN/FPS-3) radars, eleven gap-filler radars, and three height-finding radars were transmitted over telephone lines to

1782-412: The lab placed Jay Forrester in charge of the project. They soon built a large analog computer for the task, but found that it was inaccurate and inflexible. Solving these problems in a general way would require a much larger system, perhaps one so large as to be impossible to construct. Judy Clapp was an early senior technical member of this team. Perry Crawford , another member of the MIT team, saw

1836-429: The last one loaded. Whirlwind operated much like a reverse Polish notation calculator in this respect; except there was no operand stack, only an accumulator . The designers felt that 2048 words of memory would be the minimum usable amount, requiring 11 bits to represent an address, and that 16 to 32 instructions would be the minimum for another five bits — and so it was 16 bits. The Whirlwind design incorporated

1890-471: The linear region. Further, commercial manufacturers expected their tubes to only be in use for a few hours per day. To ameliorate this issue, the heaters were turned off on valves not expected to switch for long periods. The heater voltage was turned on and off with a slow ramp waveform to avoid thermal shock to the heater filaments. Even these measures were not enough to achieve the required reliability. Incipient faults were proactively sought by testing

1944-735: The machine, which became the basis for the Boston Computer Museum in 1979. Although much of the machine was lost when decommissioned, many of its components are now in the collection of the Computer History Museum in Mountain View, California and the MIT Museum . As of February 2009, a core memory unit is displayed at the Charles River Museum of Industry & Innovation in Waltham, Massachusetts . One plane of core memory, on loan from

1998-508: The mainstream with the eponymous Nintendo 64 (1996), but beyond this introduction stayed uncommon until the advent of x86-64 architectures around the year 2003, and 2014 for mobile devices with the ARMv8-A instruction set. On 32-bit processors, external data bus width continues to increase. For example, DDR1 SDRAM transfers 128 bits per clock cycle. DDR2 SDRAM transfers a minimum of 256 bits per burst. Control store A control store

2052-399: The material and assigned him to the workbench, while Forrester went back to full-time project management. (Buck would go on to invent the cryotron and content-addressable memory at the lab.) After approximately two years of further research and development, they were able to demonstrate a core plane that was made of 32 by 32, or 1024 cores, holding 1024 bits of data. Thus, they had reached

2106-444: The memory access time, the entire processor was slower than designed. Jay Forrester was desperate to find a suitable memory replacement for his computer. Initially the computer only had 32 words of storage, and 27 of these words were read-only registers made of toggle switches . The remaining five registers were flip-flop storage, with each of the five registers being made from more than 30 vacuum tubes . This "test storage", as it

2160-455: The memory was said to recirculate. Mercury delay lines operated at about the speed of sound, so were very slow in computer terms, even by the standards of the computers of the late 1940s and 1950s. The speed of sound in mercury was also very dependent on temperature. Since a delay line held a defined number of bits, the frequency of the clock had to change with the temperature of the mercury. If there were many delay lines and they did not all have

2214-487: The originally intended storage size of an electrostatic tube, a goal that had not yet been reached by the tubes themselves, only holding 512 bits per tube in the latest design generation. Very quickly, a 1024-word core memory was fabricated, replacing the electrostatic memory. The electrostatic memory design and production was summarily canceled, saving a good deal of money to be reallocated to other research areas. Two additional core memory units were later fabricated, increasing

Whirlwind I - Misplaced Pages Continue

2268-407: The same temperature at all times, the memory data could easily become corrupted. The Whirlwind designers quickly discarded the delay line as a possible memory—it was both too slow for the envisioned flight simulator, and too unreliable for a reproducible production system, for which Whirlwind was intended to be a functional prototype. The alternative form of memory was known as "electrostatic". This

2322-468: The success of these measures. Of the 1,622 7AD7 tubes in use, 243 failed, of which 168 were found by marginal testing. Of the 1,412 7AK7 tubes in use, 18 failed, of which only 2 failed during marginal checking. As a result, Whirlwind was far more reliable than any commercially available machine. Many other features of the Whirlwind tube testing regime were not standard tests and required specially built equipment. One condition that required special testing

2376-673: The system and data. Some CPU designs compile the instruction set to a writable RAM or FLASH inside the CPU (such as the Rekursiv processor and the Imsys Cjip ), or an FPGA ( reconfigurable computing ). Several Intel CPUs in the x86 architecture family have writable microcode, starting with the Pentium Pro in 1995. This has allowed bugs in the Intel Core 2 microcode and Intel Xeon microcode to be fixed in software, rather than requiring

2430-399: The total memory size available. The design used approximately 5,000 vacuum tubes . The large number of tubes used in Whirlwind resulted in a problematic failure rate since a single tube failure could cause a system failure. The standard pentode at the time was the 6AG7, but testing in 1948 determined that its expected lifetime in service was too short for this application. Consequently,

2484-403: The valves during maintenance periods. They were subject to stress tests called marginal testing because they applied voltages and signals to the valves right up to their design margins. These tests were designed to bring on early failure of valves that would otherwise have failed while in service. They were carried out automatically by a test program. The maintenance statistics for 1950 show

2538-401: Was a cathode ray tube memory, similar in many aspects to an early TV picture tube or oscilloscope tube. An electron gun sent a beam of electrons to the far end of the tube, where they impacted a screen. The beam would be deflected to land at a particular spot on the screen. The beam could then build up a negative charge at that point, or change a charge that was already there. By measuring

2592-400: Was essentially sixteen times as fast as other machines. Today, almost all CPUs perform arithmetic in "bit-parallel" mode. The word size was selected after some deliberation. The machine worked by passing in a single address with almost every instruction, thereby reducing the number of memory accesses. For operations with two operands, adding for instance, the "other" operand was assumed to be

2646-405: Was known, was intended to allow checkout of the processing elements while the main memory was not ready. The main memory was so late that the first experiments of tracking airplanes with live radar data were done using a program manually set into test storage. Forrester came across an advertisement for a new magnetic material being produced by a company. Recognizing that this had the potential to be

2700-439: Was momentary shorting on a few tubes caused by small objects like lint inside the tube. Occasional spurious short pulses are a minor problem, or even entirely unnoticeable, in analog circuits, but are likely to be disastrous in a digital circuit. These did not show up on standard tests but could be discovered manually by tapping the glass envelope. A thyratron-triggered circuit was built to automate this test. After connection to

2754-518: Was rented ($ 1/yr) from June 30, 1959, until 1974 by project member, William M. Wolf (1928-2015). The power to run the machine cost $ 2500 per month, and the Wolf Research and Development Corporation did work for the Air Force and Buckminster Fuller 's World Game . Ultimately moving Whirlwind I cost $ 250,000 and the company made $ 100,000 on it. Wolf R&D Corporation was sold to EG&G in 1967 for $ 5.5 million. Ken Olsen and Robert Everett saved

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2808-461: Was still in development, and while the goal was to hold 1024 bits per tube, this goal was never reached, even several years after the plan had called for full-size functional tubes. Also, the specifications had called for an access time of six microseconds, but the actual access time was around 30 microseconds. Since the basic cycle time of the Whirlwind ;I processor was determined by

2862-452: Was then specially developed for Whirlwind by Sylvania . Cathode poisoning is at its worst when the tube is being run in cut-off with the heater on. Commercial tubes were intended for radio (and later, television) applications where they are rarely run in this state. Analog applications like these keep the tube in the linear region, whereas digital applications switch the tube between cut-off and full conduction, passing only briefly through

2916-436: Was very successful and plans were made to make an even larger version known as TX-1. However this project was far too ambitious and had to be scaled back to a smaller version known as TX-2 . Even this version proved troublesome, and Olsen left in mid-project to start Digital Equipment Corporation (DEC). DEC's PDP-1 was essentially a collection of TX-0 and TX-2 concepts in a smaller package. After supporting SAGE, Whirlwind I

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