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40-620: The POWER1 was introduced in 1990, with the introduction of the IBM RS/6000 POWERserver servers and POWERstation workstations , which featured the POWER1 clocked at 20, 25 or 30 MHz . The POWER1 received two upgrades, one in 1991, with the introduction of the POWER1+ and in 1992, with the introduction of POWER1++. These upgraded versions were clocked higher than the original POWER1, made possible by improved semiconductor processes . The POWER1+

80-497: A floating point unit (FPU), a number of data-cache units (DCU), a storage-control unit (SCU) and an I/O unit. Due to its modular design, IBM was able to create two configurations by simply varying the number of DCUs, RIOS-1 and a RIOS.9 . The RIOS-1 configuration has four DCUs, the intended amount, and was clocked at up to 40 MHz, whereas the RIOS.9 CPU had two DCUs and was clocked at lower frequencies. The chips are mounted on

120-616: A 0.45 μm effective channel length; and one layer of polysilicon and four layers of metal interconnect. The chips are packaged in a ceramic multi-chip module (MCM) that measures 64 mm by 64 mm. An improved version of the POWER2 optimized for transaction processing was introduced in May 1994 as the POWER2+. Transaction processing workloads benefited from the addition of a L2 cache with capacities of 512 KB, 1 MB and 2 MB. This cache

160-494: A 64 KB data cache implemented through four identical data-cache units (DCU), each containing 16 KB of data cache. The cache and the buses that connect the DCU to the other chips are ECC protected. The DCUs also provide the interface to the memory. If two DCUs are present (RIOS.9 configuration), the memory bus is 64 bits wide, and if four DCUs are present (RIOS-1 configuration), the memory bus is 128 bits wide. The memory interface portion of

200-544: A IBM 9309 Rack Enclosure; this a first generation RS/6000 server running AIX. These units were configured by IBM as experimental "NSS" ("Network Switching Subsystem") routers, and used on the NSFnet T3 backbone in the early/mid-90s. Produced since 1994 until the time were the RS/6000 line was rebranded to System P. The Model N40 was a PowerPC-based laptop developed and manufactured by Tadpole Technology in conjunction with IBM. It

240-508: A die measuring approximately 160 mm. RS/6000 The RISC System/6000 ( RS/6000 ) is a family of RISC -based Unix servers , workstations and supercomputers made by IBM in the 1990s. The RS/6000 family replaced the IBM RT PC computer platform in February 1990 and is the first computer line to see the use of IBM's POWER and PowerPC based microprocessors. In October 2000,

280-464: A die measuring approximately 160 mm. The POWER1's floating point unit executes floating-point instructions issue by the ICU. The FPU is pipelined and can execute single precision (32-bit) and double precision (64-bit) instructions. It is capable of performing multiply-add instructions, which contributed to the POWER1's high floating point performance. In most processors, a multiply and an add, which

320-485: A large 4 GB address range. The POWER1 is a big-endian CPU that uses a Harvard style cache hierarchy with separate instruction and data caches. The instruction cache, referred to as the "I-cache" by IBM, is 8 KB in size and is two-way set associative with a line size of 64 bytes. The I-cache is located on the ICU chip. The data cache, referred to as the "D-cache" by IBM, is 32 KB in size for RIOS.9 configurations and 64 KB in size for RIOS-1 configurations. The D-cache

360-451: A maximum of 4 W of heat each. The total number of transistors featured by the POWER1, assuming that it is a RIOS-1 configuration, is 6.9 million, with 2.04 million used for logic and 4.86 million used for memory. The die area of all the chips combined is 1,284 mm. The total number of signal pins is 1,464. The ICU contains the instruction cache, referred to as the "I-cache" by IBM and the branch processing unit (BPU). The BPU contains

400-405: A phone number (via a modem) in case of serious failure with the machine. Early advertisements and documentation called the service processor "System Guard", (or SystemGuard ) although this name was apparently dropped later on, roughly around the same time that the simplified RS/6000 name was adopted for the computer line itself. Late in the RS/6000 cycle, the service processor was "converged" with

440-429: A prediction bit in the branch instructions, with the results discarded before being saved if the branch was not taken. The alternate instruction would be buffered and discarded if the branch was taken. Consequently, subroutine calls and interrupts are dealt with without incurring branch penalties. The condition code register has eight field sets, with the first two reserved for fixed and floating point instructions and

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480-421: A technique that improves the performance of superscalar processors but was previously reserved for mainframes . The POWER1 was also the origin for the highly successful families of POWER , PowerPC and Power ISA processors that followed it, measuring in hundreds of different implementations. The open source GCC compiler removed support for POWER1 (RIOS) and POWER2 (RIOS2) in the 4.5 release. The POWER1

520-406: Is a 32-bit two-way superscalar CPU. It contains three major execution units, a fixed-point unit (FXU), a branch unit (BPU) and a floating point unit (FPU). Although the POWER1 is a 32-bit CPU with a 32-bit physical address , its virtual address is 52 bits long. The larger virtual address space was chosen because it was beneficial for the performance of applications, allowing each one to have

560-488: Is common in technical and scientific floating-point code, cannot be executed in one cycle, as in the POWER1. Use of fused multiply–add also means that the data is only rounded once, improving the precision of the result slightly. The floating-point register file is also located on the FPU chip. It contains 32 64-bit floating-point registers, six rename registers and two registers that are used by divide instructions. The POWER1 has

600-475: Is four-way set associative with a line size of 128 bytes. The D-cache employs a store-back scheme, where data that is to be stored is written to the cache instead of the memory in order to reduce the number of writes destined for the memory. The store-back scheme is used to prevent the CPU from monopolizing access to the memory. Although the POWER1 was a high-end design, it was not capable of multiprocessing , and as such

640-458: Is less cache, the data cache unit chips are smaller as a result, and the revised storage control unit chip is also smaller. A goal for the six-chip configuration was to reduce cost, and therefore the chips are packaged in a solder ball connect (SBC) package instead of a MCM. POWER2 Super Chip (P2SC) was released in October 1996 as the successor of the POWER2. It was a single-chip implementation of

680-560: The Micro Channel interface and controls both I/O and DMA transactions between the Micro Channel adapters and the system memory. The two SLAs each implement a serial fibre optic link, which are intended to connect RS/6000 systems together. The optical links were not supported at the time of the RS/6000's release. The I/O unit contains approximately 0.5 million transistors, with 0.3 million used for logic and 0.2 million used for memory, on

720-542: The PowerPC 604e -based Deep Blue supercomputer that beat world champion Garry Kasparov at chess in 1997, and the POWER3 -based ASCI White which was the fastest supercomputer in the world during 2000–2002. Many RS/6000 and subsequent pSeries machines came with a service processor, which booted itself when power was applied and continuously ran its own firmware, independent of the operating system. The service processor could call

760-564: The RISC Single Chip (RSC), feature-reduced single-chip variant for entry-level RS/6000 systems, and the RAD6000 , a radiation-hardened variant of the RSC for space applications. An indirect derivative of the POWER1 is the PowerPC 601 , a feature-reduced variant of the RSC intended for consumer applications. The POWER1 is notable as it represented a number of firsts for IBM and computing in general. It

800-518: The program counter , the condition code register and a loop register. The ICU contains 0.75 million transistors with 0.2 million used for logic and 0.55 million used for SRAM . The ICU die measures approximately 160 mm (12.7 × 12.7 mm). The BPU was capable of dispatching multiple instructions to the fixed and floating point instructions queues while it was executing a program flow control instruction (up to four simultaneously and out of order). Speculative branches were also supported by using

840-572: The 0.25 μm CMOS-6S2 process was announced at the Microprocessor Forum in October 1997. The P2SC was not a complete copy of the POWER2, the L1 data cache and data translation lookaside buffer (TLB) capacities were halved to 128 KB and 256 entries, respectively, and a rarely used feature that locked entries in the TLB was not implemented in order to fit the original design onto a single die. The P2SC

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880-497: The DCUs provide three features that improves the reliability and availability of the memory: memory scrubbing , ECC and bit steering . Each DCU contains approximately 1.125 million transistors, with 0.175 million used for logic and 0.95 million used for SRAM, on a die measuring approximately 130 mm² (11.3 × 11.3 mm). The POWER1 is controlled by the SCU chip. All communications between

920-567: The FXU contains the POWER1's fixed-point register file, an arithmetic logic unit (ALU) for general instructions, and a dedicated fixed-point multiply and divide unit. It also contains instruction buffers that receive both fixed- and floating-point instructions from the ICU, passing on the floating-point instructions to the FPU, and a 128-entry two-way set-associative D- TLB for address translation. The FXU contains approximately 0.5 million transistors, with 0.25 million used for logic and 0.25 used for memory, on

960-542: The ICU, FXU and DCU chips as well as the memory and I/O devices is arbitrated by the SCU. Although the DCUs provide the means to perform memory scrubbing, it is the SCU that controls the process. The SCU contains approximately 0.23 million transistors, all of them for logic, on a die measuring approximately 130 mm. The POWER1's I/O interfaces are implemented by the I/O unit, which contains an I/O channel controller (IOCC) and two serial link adapters (SLAs). The IOCC implements

1000-460: The POWER instruction set architecture (consisting of new user and system instructions and other system-related features), higher clock rates (55 to 71.5 MHz), an extra fixed point unit and floating point unit , a larger 32 KB instruction cache, and a larger 128 or 256 KB data cache. The POWER2 was a multi-chip design consisting of six or eight semi-custom integrated circuits, depending on

1040-519: The POWER2 was the fastest microprocessor, surpassing the Alpha 21064 . When the Alpha 21064A was introduced in 1993, the POWER2 lost the lead and became second. IBM claimed that the performance for a 62.5 MHz POWER2 was 73.3 SPECint92 and 134.6 SPECfp92. The open source GCC compiler removed support for POWER1 (RIOS) and POWER2 (RIOS2) in the 4.5 release. Improvements over the POWER1 included enhancements to

1080-588: The RS/6000 brand was retired for POWER-based servers and replaced by the eServer pSeries . Workstations continued under the RS/6000 brand until 2002, when new POWER-based workstations were released under the IntelliStation POWER brand. The first RS/6000 models used the Micro Channel bus, later models used PCI . Some later models conformed to the PReP and CHRP standard platforms, which were co-developed with Apple and Motorola , with Open Firmware . The plan

1120-546: The amount of data cache (the 256 KB configuration required eight chips). The partitioning of the design was identical to that of the POWER1: an instruction cache unit chip, a fixed-point unit chip, a floating-point unit chip, a storage control unit chip, and two or four data cache unit chips. The eight-chip configuration contains a total of 23 million transistors and a total die area of 1,215 mm . The chips are manufactured by IBM in its 0.72 μm CMOS process, which features

1160-521: The eight-chip POWER2, integrating 15 million transistors on a 335 mm die manufactured in IBM's 0.29 μm five-layer metal CMOS-6S process. The first version ran at 120 or 135 MHz, nearly twice as fast as the POWER2 at 71.5 MHz, with the memory and I/O buses running at half speed to support the higher clock frequency. IBM claimed that the performance of this version was 5.5 SPECint95_base and 14.5 SPECfp95_base. A faster 160 MHz part fabricated in

1200-521: The one used on the AS/400 machines. POWER machines typically ran AIX . Solaris, OS/2 and Windows NT were also ported to PowerPC. Later Linux was also used. Some AIX systems support IBM Web-based System Manager . Some models were marketed under the RS/6000 POWERstation and POWERserver names. The early lines were based on an IBM proprietary Micro Channel architecture ; the same architecture that

1240-461: The seventh for vector instructions . The rest of the fields could be used by other instructions. The loop register is a counter for "decrement and branch on zero" loops with no branch penalty, a feature similar to those found in some DSPs such as the TMS320C30. The FXU is responsible for decoding and executing all fixed-point instructions and floating-point load and store instructions. For execution,

POWER1 - Misplaced Pages Continue

1280-612: The “CPU planar”, a printed circuit board (PCB), using through-hole technology. Due to the large number of chips with wide buses , the PCB has eight planes for routing wires, four for power and ground and four for signals. There are two signal planes on each side of the board, while the four power and ground planes are in the center. The chips that make up the POWER1 are fabricated in a 1.0 μm CMOS process with three layers of interconnect. The chips are packaged in ceramic pin grid array (CPGA) packages that can have up to 300 pins and dissipate

1320-481: Was IBM's first RISC processor intended for high-end applications (the ROMP was considered a commercial failure and was not used in high-end workstations), it was the first to implement the then new POWER instruction set architecture and it was IBM's first successful RISC processor. For computing firsts, the POWER1 would be known for being the first CPU to implement some form of register renaming and out-of-order execution ,

1360-505: Was clocked slightly higher than the original POWER1, at frequencies of 25, 33 and 41 MHz, while the POWER1++ took the microarchitecture to its highest frequencies — 25, 33, 41.6, 45, 50 and 62.5 MHz. In September 1993, the POWER1 and its variants was succeeded by the POWER2 (known briefly as the "RIOS2"), an evolution of the POWER1 microarchitecture. The direct derivatives of the POWER1 are

1400-403: Was disadvantaged, as the only way performance could be improved was by clocking the CPU higher, which was difficult to do with such a large multi-chip design. IBM used clustering to overcome this disadvantage in POWER1 systems, allowing them to effectively function as if they were multiprocessing systems, a concept proven by the popularity of SP1 supercomputers based on the POWER1. As the POWER1

1440-425: Was implemented off-package with industry-standard burst SRAMs. The cache was connected to the POWER2+ via a 64- (for low-end systems) or 128-bit bus (for high-end systems). The cache was direct-mapped , had a 128-byte line size, and was write-through . The cache tags were contained on the storage control unit chip. The POWER2+ has a narrower 64- or 128-bit memory bus and a smaller 64 or 128 KB data cache. As there

1480-635: Was released on 25 March 1994, priced at US$ 12,000. The internal batteries could power the system for 45 minutes only and an external battery pack that lasted for 4 hours was available for this reason. POWER2#P2SC The POWER2 , originally named RIOS2 , is a processor designed by IBM that implemented the POWER instruction set architecture . The POWER2 was the successor of the POWER1 , debuting in September 1993 within IBM's RS/6000 systems. When introduced,

1520-400: Was the basis of the POWER2 and P2SC microprocessors, the lack of multiprocessing was passed on to these later POWER processors. Multiprocessing was not supported until the introduction of the POWER3 in 1998. The POWER1 is a multi-chip CPU built from separate chips that are connected to each other by buses. The POWER1 consists of an instruction-cache unit (ICU), a fixed-point unit (FXU),

1560-667: Was to enable the RS/6000 to run multiple operating systems such as Windows NT , NetWare , OS/2 , Solaris , Taligent , AIX and Mac OS but in the end only IBM's Unix variant AIX was used and supported on RS/6000. Linux is widely used on CHRP based RS/6000s, but support was added after the RS/6000 name was changed to eServer pSeries in 2000. The RS/6000 family also included the POWERserver servers, POWERstation workstations and Scalable POWERparallel supercomputer platform. While most machines were desktops, desksides, or rack-mounted, there were laptop models too. Famous RS/6000s include

1600-468: Was used in the high end PS/2 x86 desktop line. MCA-based lines were produced until 1999. These workstations were marketed under the PowerStation name. This type was for Xstations, IBM's line of X terminal . The 380, 390, and 39H servers correspond to the 3AT, 3BT, and 3CT workstations. The 7016-730 model was a version of 7013-530 model, but with licensed by Silicon Graphics graphics card. Uses

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