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62-600: The Data General Nova was intended to outperform the PDP-8 while being less expensive, and in a similar fashion, the Eclipse was meant to compete against the larger PDP-11 computers. It kept the simple register architecture of the Nova but added a stack pointer which the Nova lacked. The stack pointer was added back to the later Nova 3 machines in 1975 and also used on the later 32-bit Data General Eclipse MV/8000 . The AOS operating system

124-414: A "prefetcher" to increase performance by fetching up to 11 instructions from memory before they were needed. Data General also produced a series of microNOVA single-chip implementations of the Nova processor. To allow it to fit into a 40-pin dual in-line package (DIP) chip, the address bus and data bus shared a set of 16 pins. This meant that reads and writes to memory required two cycles, and that

186-404: A centrally located "board-on-a-board", 5.25" wide by 6.125" high, and was covered by a protective plate. It was surrounded by the necessary support driver read-write-rewrite circuitry. All of the core and the corresponding support electronics fit onto a single standard 15 x 15-inch (380 mm) board. Up to 32K of such core RAM could be supported in one external expansion box. Semiconductor ROM

248-448: A consortium of venture capital funds from the Boston area, who agreed to provide an initial US$ 400,000 investment with a second US$ 400,000 available for production ramp-up. de Castro, Burkhart and Sogge quit DEC and started Data General (DG) on 15 April 1968. Green did not join them, considering the venture too risky, and Richman did not join until the product was up and running later in

310-476: A demonstration of the power of their Micromatrix gate array technology, in 1968 Fairchild prototyped the 4711, a single-chip 4-bit ALU. The design was never intended for mass production and was quite expensive to produce. The introduction of the Signetics 8260 in 1969 forced their hand; both Texas Instruments and Fairchild introduced 4-bit ALUs of their own in 1970, the 74181 and 9341, respectively. In contrast to

372-530: A divisional manager; Richard Sogge, another hardware engineer; and Henry Burkhardt III, a software engineer. In contrast to the PDP-X, the new effort focused on a single machine that could be brought to market quickly, as de Castro felt the PDP-X concept was far too ambitious for a small startup company . Discussing it with the others at DEC, the initial concept led to an 8-bit machine which would be less costly to implement. The group began talking with Herbert Richman,

434-453: A fault to the module level, and a defective or suspected faulty module would be replaced by a known-good one, to repair a malfunctioning computer system. The plastic handles were color-coded to distinguish the various circuit design families used by the modules, and thus their power supply voltages, logic signal voltages, and switching speed. The trademark "Flip-Chip"' was filed on August 27, 1964. Various manuals produced by DEC refer to

496-665: A handle adding 1/2 inch. Double-height modules with two connectors side by side were 5-3/16 inches wide. Later, when two-sided boards were introduced, upwards-compatible double-sided 36-contact edge connectors were used, but the basic connector and board dimensions remained unchanged. If more component real estate area were required for electronic circuitry, the "standard-length" modules would be supplemented by "extended-length" modules. The company eventually produced extended-length quad-height (four connectors) and hex-height (six connectors) modules as larger circuit boards came into use; these larger boards often included metal levers to handle

558-454: A matching high-performance version. Gruner's low-cost model launched in 1970 as the Nova 1200 , the 1200 referring to the use of the original Nova's 1,200 ns core memory. It featured a 4-bit ALU based on a single 74181 chip, and was thus essentially a repackaged Nova. Seligman's repackaged four-ALU SuperNOVA was released in 1971 as the Nova 800 , resulting in the somewhat confusing naming where

620-466: A salesman for Fairchild Semiconductor who knew the others through his contacts with DEC. At the time, Fairchild was battling with Texas Instruments and Signetics in the rapidly growing TTL market and were introducing new fabs that allowed more complex designs. Fairchild's latest 9300 series allowed up to 96 gates per chip, and they had used this to implement a number of 4-bit chips like binary counters and shift registers . Using these ICs reduced

682-408: A separate slot. An additional option allowed for memory mapping, allowing programs to access up to 128 kwords of memory using bank switching . Unlike the earlier machines, the Nova 4 did not include a front panel console and instead included a ROM containing machine code that allows a terminal to emulate a console when needed. There were three different versions of the Nova 4, the Nova 4/C,

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744-477: A thermal printer, and a 9-track tape drive. Its primary purpose was to download an image of either the Cray Operating System or customer engineering diagnostics at boot time. Once booted, it acted as a status and control console via RDOS station software . This minicomputer -related article is a stub . You can help Misplaced Pages by expanding it . Data General Nova The Data General Nova

806-454: Is a diverse but ardent group of people worldwide who restore and preserve original 16-bit Data General systems. The Nova, unlike the PDP-8 , was a load–store architecture . It had four 16-bit accumulator registers, two of which (2 and 3) could be used as index registers . There was a 15-bit program counter and a single-bit carry register. As with the PDP-8, current + zero page addressing

868-473: Is a series of 16-bit minicomputers released by the American company Data General . The Nova family was very popular in the 1970s and ultimately sold tens of thousands of units. The first model, known simply as "Nova", was released in 1969. The Nova was packaged into a single 3U rack-mount case and had enough computing power to handle most simple tasks. The Nova became popular in science laboratories around

930-450: The PDP-11 , a much more complex design that was as different from the PDP-X as the Nova was. The two designs competed heavily in the market. Rumors of the new system from DEC reached DG shortly after the Nova began shipping. In spring 1970 they hired a new designer, Larry Seligman, to leapfrog any possible machine in the making. Two major changes had taken place since the Nova was designed; one

992-487: The input/output circuitry and a complete system typically included another board with 4 kB of random-access memory . A complete four-card system fit in a single rackmount chassis. The boards were designed so they could be connected together using a printed circuit backplane , with minimal manual wiring, allowing all the boards to be built in an automated fashion. This greatly reduced costs over 8/I, which consisted of many smaller boards that had to be wired together at

1054-460: The "program load" switch was flipped. Versions were available with four ("2/4"), seven and ten ("2/10") slots. The Nova 3 of 1975 added two more registers, used to control access to a built-in stack. The processor was also re-implemented using TTL components, further increasing the performance of the system. The Nova 3 was offered in four-slot (the Nova 3/4) and twelve-slot (the Nova 3/12) versions. It appears that Data General originally intended

1116-546: The 8260, the new designs offered all common logic functions and further reduced the chip count. This led DG to consider the design of a new CPU using these more integrated ICs. At a minimum, this would reduce the CPU to a single card for either the basic Nova or the SuperNOVA. A new concept emerged where a single chassis would be able to host either machine simply by swapping out the CPU circuit board. This would allow customers to purchase

1178-646: The Eclipse resulted in the Eclipse MV series of the 1980s. Edson de Castro was the Product Manager of the pioneering Digital Equipment Corporation (DEC) PDP-8 , a 12-bit computer widely referred to as the first true minicomputer. He also led the design of the upgraded PDP-8/I, which used early integrated circuits in place of individual transistors. During the PDP-8/I process, de Castro had been visiting circuit board manufacturers who were making rapid advances in

1240-458: The Eclipse was originally intended to replace the Nova outright, also evidenced by the fact that the Nova 3 series released at the same time was phased out the next year. However, strong continuing demand resulted in the Nova 4, perhaps as a result of the continuing problems with the Eclipse. The original Cray-1 system used an Eclipse to act as a Maintenance and Control Unit (MCU). It was configured with two Ampex CRTs, an 80 MB Ampex disk drive,

1302-469: The Nova 3 to be the last of its line, planning to replace the Nova with the later Eclipse machines. However, continued demand led to a Nova 4 machine introduced in 1978, this time based on four AMD Am2901 bit-slice ALUs . This machine was designed from the start to be both the Nova 4 and the Eclipse S/140, with different microcode for each. A floating-point co-processor was also available, taking up

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1364-413: The Nova 4/S and the Nova 4/X. The Nova 4/C was a single-board implementation that included all of the memory (16 or 32 kwords). The Nova 4/S and 4/X used separate memory boards. The Nova 4/X had the on-board memory management unit (MMU) enabled to allow up to 128 kwords of memory to be used. The MMU was also installed in the Nova 4/S, but was disabled by firmware. Both the 4/S and the 4/X included

1426-436: The Nova computers, running under a range of consistent operating systems. FORTRAN IV , ALGOL , Extended BASIC, Data General Business Basic , Interactive COBOL , and several assemblers were available from Data General. Third-party vendors and the user community expanded the offerings with Forth , Lisp , BCPL , C , ALGOL , and other proprietary versions of COBOL and BASIC . The machine instructions implemented below are

1488-456: The Nova simple compared to competing machines. In addition to its dedicated I/O bus structure, the Nova backplane had wire wrap pins that could be used for non-standard connectors or other special purposes. The instruction format could be broadly categorized into one of three functions: 1) register-to-register manipulation, 2) memory reference, and 3) input/output. Each instruction was contained in one word. The register-to-register manipulation

1550-510: The SuperNova. Future versions of the system added a stack unit and hardware multiply/divide. The Nova 4 / Eclipse S/140 was based on four AMD 2901 bit-slice ALUs, with microcode in read-only memory , and was the first Nova designed for DRAM main memory only, without provision for magnetic-core memory . The first models were available with 8 K words of magnetic-core memory as an option, one that practically everyone had to buy, bringing

1612-463: The backplane, which was itself connected together using wire wrap . The larger-board construction also made the Nova more reliable, which made it especially attractive for industrial or lab settings. The new design used a simple load–store architecture which would reemerge in the RISC designs in the 1980s. Because the complexity of a flip-flop was being rapidly reduced as they were implemented in chips,

1674-458: The common set implemented by all of the Nova series processors. Specific models often implemented additional instructions, and some instructions were provided by optional hardware. All arithmetic instructions operated between accumulators. For operations requiring two operands, one was taken from the source accumulator, and one from the destination accumulator, and the result was deposited in the destination accumulator. For single-operand operations,

1736-420: The company had annual sales of US$ 100 million . Ken Olsen had publicly predicted that DG would fail, but with the release of the Nova it was clear that was not going to happen. By this time, a number of other companies were talking about introducing 16-bit designs as well. Olsen decided these presented a threat to their 18-bit line as well as 12-bit, and began a new 16-bit design effort. This emerged in 1970 as

1798-455: The complexity of the boards they could assemble. de Castro concluded that the 8/I could be produced using fully automated assembly on large boards, which would have been impossible only a year earlier. Others within DEC had become used to the smaller boards used in earlier machines and were concerned about tracking down problems when there were many components on a single board. For the 8/I, the decision

1860-460: The core with read-only memory ; lacking core's read–write cycle, this could be accessed in 300 ns for a dramatic performance boost. The resulting machine, known as the SuperNOVA , was released in 1970. Although the initial models still used core, the entire design was based on the premise that faster semiconductor memories would become available and the platform could make full use of them. This

1922-605: The design of both the Xerox Alto (1973) and Apple I (1976) computers, and its architecture was the basis for the Computervision CGP (Computervision Graphics Processor) series. Its external design has been reported to be the direct inspiration for the front panel of the MITS Altair (1975) microcomputer. Data General followed up on the success of the original Nova with a series of faster designs. The Eclipse family of systems

Data General Eclipse - Misplaced Pages Continue

1984-468: The design offset the lack of addressing modes of the load–store design by adding four general-purpose accumulators , instead of the single register that would be found in similar low-cost offerings like the PDP series. Late in 1967, Richman introduced the group to New York-based lawyer Fred Adler, who began canvassing various funding sources for seed capital. By 1968, Adler had arranged a major funding deal with

2046-513: The entire chipset to a single VLSI . This was offered in two machines, the microNOVA MP/100 and larger microNOVA MP/200 . The microNOVA was later re-packaged with a monitor in a PC-style case with two floppy disks as the Enterprise . Enterprise shipped in 1981, running RDOS , but the introduction of the IBM PC the same year made most other machines disappear under the radar. The Nova influenced

2108-507: The larger forces need to insert or extract the boards from mating backplane connectors. The circuit boards (modules) were assembled into larger systems by plugging them into backplanes composed of blocks of connectors. These connectors were in turn interconnected by wirewrapping . (The earlier DEC System Modules used a hand-wired and soldered backplane. Manufacturing difficulties with this led DEC to investigate Gardner-Denver's automated wirewrap technology.) Troubleshooting would narrow down

2170-409: The lower-cost system and then upgrade at any time. While Seligman was working on the SuperNOVA, the company received a letter from Ron Gruner stating "I've read about your product, I've read your ads, and I'm going to work for you. And I'm going to be at your offices in a week to talk to you about that." He was hired on the spot. Gruner was put in charge of the low-cost machine while Seligman designed

2232-502: The lower-numbered model has higher performance. Both models were offered in a variety of cases, the 1200 with seven slots, the 1210 with four and the 1220 with fourteen. By this time, the PDP-11 was finally shipping. It offered a much richer instruction set architecture than the deliberately simple one in the Nova. Continuing improvement in IC designs, and especially their price–performance ratio ,

2294-401: The machine ran about half the speed of the original Nova as a result. The first chip in the series was the mN601 , of 1977. This was sold both as a CPU for other users, a complete chipset for those wanting to implement a computer, a complete computer on a single board with 4 kB of RAM, and as a complete low-end model of the Nova. An upgraded version of the design, 1979's mN602 , reduced

2356-458: The midst of a strike in the airline industry and the machine never arrived. They sent a second example, which arrived promptly as the strike had ended by that point, and in May the original one was finally delivered as well. The system was successful from the start, with the 100th being sold after six months, and the 500th after 15 months. Sales accelerated as newer versions were introduced, and by 1975

2418-582: The modules as "FLIP CHIP", "FLIP-CHIP", "Flip Chip", and "Flip-Chip", with trademark and registered trademark symbols. Some of these modules, for example, the R107 module shown, used hybrid integrated circuits built where individual diode chips were mounted on a ceramic substrate. Some boards containing flip chip modules were etched and drilled to allow those modules to be replaced by discrete components. At some points during production, conventional discrete components may have replaced these flip-chip devices, but

2480-507: The new ICs allowed the ALU to be expanded to full 16-bit width on the same two cards, allowing it to carry out math and logic operations in a single cycle and thereby making the new design four times as fast as the original. In addition, new smaller core memory was used that improved the cycle time from the original's 1,200 ns to 800 ns, offering a further ⁠ 1 / 3 ⁠ improvement. Performance could be further improved by replacing

2542-593: The operand was taken from the source register and the result replaced the destination register. For all single-operand opcodes, it was permissible for the source and destination accumulators to be the same, and the operation functioned as expected. Flip-Chip module A Flip-Chip module is a component of digital logic systems made by the Digital Equipment Corporation (DEC) for its PDP-7 , PDP-8 , PDP-9 , and PDP-10 computers, and related peripherals , beginning on August 24, 1964. As used by DEC,

Data General Eclipse - Misplaced Pages Continue

2604-450: The system cost up to $ 7,995. This core memory board was organized in planar fashion as four groups of four banks, each bank carrying two sets of core in a 64 by 64 matrix; thus there were 64 x 64 = 4096 bits per set, x 2 sets giving 8,192 bits, x 4 banks giving 32,768 bits, x 4 groups giving a total of 131,072 bits, and this divided by the machine word size of 16 bits gave 8,192 words of memory. The core on this 8K word memory board occupied

2666-401: The term described a proprietary way to package electronic circuitry which was used for central processing units , peripheral controllers, and many other digital or analog electronic products produced by the company. The first flip-chip modules mated with single-sided 18-contact card edge connectors with contacts on 1/8 inch centers. Circuit boards were 2-7/16 inches wide by 5 inches long, with

2728-459: The total IC count needed to implement a complete arithmetic logic unit (ALU), the core mathematical component of a CPU, allowing the expansion from an 8-bit design to 16-bit. This did require the expansion of the CPU from a single 15 by 15 inches (38 cm × 38 cm) printed circuit board to two, but such a design would still be significantly cheaper to produce than the 8/I while still being more powerful and ASCII-based. A third board held

2790-411: The world. It was followed the next year by the SuperNOVA , which ran roughly four times as fast, making it the fastest mini for several years. Introduced during a period of rapid progress in integrated circuit (or "microchip") design, the line went through several upgrades over the next five years, introducing the 800 and 1200, the Nova 2, Nova 3, and ultimately the Nova 4. A single-chip implementation

2852-504: The world." The basic model was not very useful out of the box, and adding 8  kW ( 16  kB ) RAM in the form of core memory typically brought the price up to US$ 7,995 . In contrast, an 8/I with 4  kW ( 6 kB ) was priced at US$ 12,800 . The first sale was to a university in Texas, with the team hand-building an example which shipped out in February. However, this was in

2914-552: The year. Work on the first system took about nine months, and the first sales efforts started that November. They had a bit of luck because the Fall Joint Computer Conference had been delayed until December that year, so they were able to bring a working unit to San Francisco where they ran a version of Spacewar! . DG officially released the Nova in 1969 at a base price of US$ 3,995 (equivalent to $ 33,193 in 2023), advertising it as "the best small computer in

2976-443: Was almost RISC -like in its bit-efficiency; and an instruction that manipulated register data could also perform tests, shifts and even elect to discard the result. Hardware options included an integer multiply and divide unit, a floating-point unit (single and double precision), and memory management . The earliest Nova came with a BASIC interpreter on punched tape . As the product grew, Data General developed many languages for

3038-440: Was already available at the time, and RAM-less systems (i.e. with ROM only) became popular in many industrial settings. The original Nova machines ran at approximately 200 kHz , but its SuperNova was designed to run at up to 3 MHz when used with special semiconductor main memory. The standardized backplane and I/O signals created a simple, efficient I/O design that made interfacing programmed I/O and Data Channel devices to

3100-601: Was also introduced as the microNOVA in 1977, but did not see widespread use as the market moved to new microprocessor designs. Fairchild Semiconductor also introduced a microprocessor version of the Nova in 1977, the Fairchild 9440 , but it also saw limited use in the market. The Nova line was succeeded by the Data General Eclipse , which was similar in most ways but added virtual memory support and other features required by modern operating systems . A 32-bit upgrade of

3162-407: Was central. There was no stack register , but later Eclipse designs would utilize a dedicated hardware memory address for this function. The earliest models of the Nova processed math serially in 4-bit packets, using a single 74181 bitslice ALU . A year after its introduction, this design was improved to include a full 16-bit parallel math unit using four 74181s, this design being referred to as

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3224-437: Was convinced that it was possible to improve upon the PDP-8 by building a 16-bit minicomputer CPU on a single 15-inch square board. In 1967, de Castro began a new design effort known as "PDP-X" which included several advanced features. Among these was a single underlying design that could be used to build 8-, 16-, and 32-bit platforms. This progressed to the point of producing several detailed architecture documents. Ken Olsen

3286-421: Was eroding the value of the original simplified instructions. Seligman was put in charge of designing a new machine that would be compatible with the Nova while offering a much richer environment for those who wanted it. This concept shipped as the Data General Eclipse series, which offered the ability to add additional circuitry to tailor the instruction set for scientific or data processing workloads. The Eclipse

3348-479: Was introduced later the same year as the SuperNOVA SC , featuring semiconductor (SC) memory. The much higher performance memory allowed the CPU, which was synchronous with memory, to be further increased in speed to run at a 300 ns cycle time (3.3 MHz). This made it the fastest available minicomputer for many years. Initially the new memory was also very expensive and ran hot, so it was not widely used. As

3410-604: Was later introduced with an extended upwardly compatible instruction set, and the MV-series further extended the Eclipse into a 32-bit architecture to compete with the DEC VAX . The development of the MV-series was documented in Tracy Kidder 's popular 1981 book, The Soul of a New Machine . Data General itself would later evolve into a vendor of Intel processor-based servers and storage arrays, eventually being purchased by EMC . There

3472-488: Was made to stay with small boards, using the new " flip-chip " packaging for a modest improvement in density. During the period when the PDP-8 was being developed, the introduction of ASCII and its major update in 1967 led to a new generation of designs with word lengths that were multiples of 8 bits rather than multiples of 6 bits as in most previous designs. This led to mid-range designs working at 16-bit word lengths instead of DEC's current 12- and 18-bit lineups. de Castro

3534-408: Was not supportive of this project, feeling it did not offer sufficient advantages over the 12-bit PDP-8 and the 18-bit PDP-9 . It was eventually canceled in the spring of 1968. Cancelation of the PDP-X prompted de Castro to consider leaving DEC to build a system on his own. He was not alone; in late 1967 a group of like-minded engineers formed to consider such a machine. The group included Pat Green,

3596-446: Was quite sophisticated, advanced compared to the PDP-11 offerings, with access control lists (ACLs) for file protection. Production problems with the Eclipse led to a rash of lawsuits in the late 1970s, after new versions of the machine were pre-ordered by many DG customers and then never arrived. After over a year of waiting, some decided to sue the company, while others simply cancelled their orders and went elsewhere. It appeared that

3658-607: Was successful in competing with the PDP-11 at the higher end of the market. Around the same time, rumors of a new 32-bit machine from DEC began to surface. DG decided they had to have a similar product, and Gruner was put in charge of what became the Fountainhead Project. Given the scope of the project, they agreed that the entire effort should be handled off-site, and Gruner selected a location at Research Triangle Park in North Carolina . This design became very complex and

3720-445: Was that Signetics had introduced the 8260, a 4-bit IC that combined an adder, XNOR and AND, meaning the number of chips needed to implement the basic logic was reduced by about three times. Another was that Intel was aggressively talking up semiconductor-based memories, promising 1024 bits on a single chip and running at much higher speeds than core memory. Seligman's new design took advantage of both of these improvements. To start,

3782-406: Was the Nova 2 , with the first versions shipping in 1973. The Nova 2 was essentially a simplified version of the earlier machines as increasing chip densities allowed the CPU to be reduced in size. While the SuperNOVA used three 15×15" boards to implement the CPU and its memory, the Nova 2 fitted all of this onto a single board. ROM was used to store the boot code, which was then copied into core when

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3844-419: Was ultimately canceled years later. While these efforts were underway, work on the Nova line continued. The 840, first offered in 1973, also included a new paged memory system allowing for addresses of up to 17-bits. An index offset the base address into the larger 128 kword memory. Actually installing this much memory required considerable space; the 840 shipped in a large 14-slot case. The next version

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