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36-442: Unlike the original Eurocard solutions such as VME , which use connectors with a 0.1 inch (2.54 mm) pin spacing, CompactPCI cards use metric connectors with a 2-millimeter pin spacing, designed to the IEC 1076 standard. 3U boards have a 110-pin connector (J1), which carries the 32-bit PCI bus signals, and an optional 110-pin connector (J2), which carries either user-defined I/O or

72-655: A and c can be used by a secondary bus, for example the STEbus . 16-bit In computer architecture , 16-bit integers , memory addresses , or other data units are those that are 16 bits (2 octets ) wide. Also, 16-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers , address buses , or data buses of that size. 16-bit microcomputers are microcomputers that use 16-bit microprocessors . A 16-bit register can store 2 different values. The range of integer values that can be stored in 16 bits depends on

108-622: A few products adopted it, including the IBM System 9000 instrument controller and the Automatix robot and machine vision systems. Kister was later joined by John Black, who refined the specifications and created the VERSAmodule product concept. A young engineer working for Black, Julie Keahey designed the first VERSAmodule card, the VERSAbus Adaptor Module, used to run existing cards on

144-467: A full 64-bit bus in 6U-sized cards and 32-bit in 3U cards. The VME64 protocol has a typical performance of 40 MB /s. Other associated standards have added hot-swapping ( plug-and-play ) in VME64x , smaller 'IP' cards that plug into a single VMEbus card, and various interconnect standards for linking VME systems together. In the late 1990s, synchronous protocols proved to be favourable. The research project

180-709: A similar fashion, later 68000-family members, starting with the Motorola 68020 , had 32-bit ALUs. One may also see references to systems being, or not being, 16-bit based on some other measure. One common one is when the address space is not the same size of bits as the internal registers. Most 8-bit CPUs of the 1970s fall into this category; the MOS 6502 , Intel 8080 , Zilog Z80 and most others had 16-bit address space which provided 64 KB of address space. This also meant address manipulation required two instruction cycles. For this reason, most processors had special 8-bit addressing modes,

216-521: A variety of technologies including Hot Swap (PICMG 2.1), Telephony signaling (PICMG 2.5) and most notably the expansion of the architecture to include switched Ethernet (PICMG 2.16). Originally designed to support the PCI signaling protocol (and hence the name "CompactPCI"), CompactPCI has grown to include a variety of technologies centered on the application of the 2mm HM connector on the 3U and 6U form factor. In fact many systems are implemented with no PCI bus on

252-449: Is a computer bus standard physically based on Eurocard sizes. In 1979, during development of the Motorola 68000 CPU, one of their engineers, Jack Kister, decided to set about creating a standardized bus system for 68000-based systems. The Motorola team brainstormed for days to select the name VERSAbus. VERSAbus cards were large, 370 by 230 mm ( 14 + 1 ⁄ 2 by 9 + 1 ⁄ 4  in), and used edge connectors . Only

288-516: Is a considerable amount of complexity added in order to support various transfer types and master/slave selection. For instance, with the ISA bus , both of these features had to be added alongside the existing "channels" model, whereby all communications was handled by the host CPU . This makes VME considerably simpler at a conceptual level while being more powerful, though it requires more complex controllers on each card. When developing and/or troubleshooting

324-416: Is sometimes called 16-bit because of the way it handles basic arithmetic. The instruction set was based on 32-bit numbers and the internal registers were 32 bits wide, so by common definitions, the 68000 is a 32-bit design. Internally, 32-bit arithmetic is performed using two 16-bit operations, and this leads to some descriptions of the system as 16-bit, or "16/32". Such solutions have a long history in

360-495: Is that, while VME is very 68000-like, the 68000 is generic enough to make this not an issue in most cases. Like the 68000, VME uses separate 32-bit data and address buses. The 68000 address bus is actually 24-bit and the data bus 16-bit (although it is 32/32 internally) but the designers were already looking towards a full 32-bit implementation. In order to allow both bus widths, VME uses two different Eurocard connectors, P1 and P2. P1 contains three rows of 32 pins each, implementing

396-451: The 386SX , which is a 32-bit processor with 32-bit ALU and internal 32-bit data paths with a 16-bit external bus and 24-bit addressing of the processor it replaced. In the context of IBM PC compatible and Wintel platforms, a 16-bit application is any software written for MS-DOS , OS/2 1.x or early versions of Microsoft Windows which originally ran on the 16-bit Intel 8088 and Intel 80286 microprocessors . Such applications used

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432-673: The Intel 80286 , the WDC 65C816 , and the Zilog Z8000 . The Intel 8088 was binary compatible with the Intel 8086, and was 16-bit in that its registers were 16 bits wide, and arithmetic instructions could operate on 16-bit quantities, even though its external bus was 8 bits wide. 16-bit processors have been almost entirely supplanted in the personal computer industry, and are used less than 32-bit (or 8-bit) CPUs in embedded applications. The Motorola 68000

468-513: The integer representation used. With the two most common representations, the range is 0 through 65,535 (2 − 1) for representation as an ( unsigned ) binary number , and −32,768 (−1 × 2 ) through 32,767 (2 − 1) for representation as two's complement . Since 2 is 65,536, a processor with 16-bit memory addresses can directly access 64 KB (65,536 bytes) of byte-addressable memory. If a system uses segmentation with 16-bit segment offsets, more can be accessed. The MIT Whirlwind ( c. 1951)

504-517: The zero page , improving speed. This sort of difference between internal register size and external address size remained in the 1980s, although often reversed, as memory costs of the era made a machine with 32-bit addressing, 2 or 4 GB, a practical impossibility. For example, the 68000 exposed only 24 bits of addressing on the DIP , limiting it to a still huge (for the era) 16 MB. A similar analysis applies to Intel's 80286 CPU replacement, called

540-607: The 1960s, especially on minicomputer systems. Early 16-bit computers ( c. 1965–70) include the IBM 1130 , the HP 2100 , the Data General Nova , and the DEC PDP-11 . Early 16-bit microprocessors , often modeled on one of the mini platforms, began to appear in the 1970s. Examples ( c. 1973–76) include the five-chip National Semiconductor IMP-16 (1973), the two-chip NEC μCOM-16 (1974),

576-480: The 68000's ecosystem agreed to use the standard, including Signetics, Philips, Thomson, and Mostek. Soon it was officially standardized by the IEC as the IEC 821 VMEbus and by ANSI and IEEE as ANSI/IEEE 1014-1987. The original standard was a 16-bit bus, designed to fit within the existing Eurocard DIN connectors. However, there have been several updates to the system to allow wider bus widths. The current VME64 includes

612-477: The CompactPCI card operates on a particular VIO voltage the card shall have the respective coloured coding key. If the card is compatible with both voltages then it may not have any coding key. The image above illustrates a 5 V VIO 8-slot backplane. CompactPCI was initially ratified as PICMG 2.0 in late 1995 as a passive backplane for PCI signaling. The 2.x series of specifications from PICMG provide support for

648-465: The VME bus, examination of hardware signals can be very important. Logic analyzers and bus analyzers are tools that collect, analyze, decode, store signals so people can view the high-speed waveforms at their leisure. VITA offers a comprehensive FAQ to assist with the front end design and development of VME systems. Computers using VMEbus include: Seen looking into backplane socket. P1 P2 P2 rows

684-457: The VMEbus. They also placed Revision A of the specification in the public domain. In 1985, Aitech developed, under contract for US Army TACOM , the first conduction-cooled 6U VMEbus board. Although electrically providing a compliant VMEbus protocol interface, mechanically, this board was not interchangeable for use in air-cooled lab VMEbus development chassis. In late 1987, a technical committee

720-558: The backplane, such as those implemented with switched Ethernet board interconnection (PICMG 2.16). A drawback of the design is that the signal pins can become bent when a new device is inserted. Related standards include CompactPCI Express and CompactPXI , which follow a similar concept, but substitute the protocols and signaling of PCI Express and PXI respectively. The abbreviations cPCI , CPCI , cPCIe , and CPCIe are colloquial terms and are not officially used by PICMG. VMEbus VMEbus ( Versa Module Eurocard bus)

756-410: The backplane. Address modifiers specify the number of significant address bits, the privilege mode (to allow processors to distinguish between bus accesses by user-level or system-level software), and whether or not the transfer is a block transfer. Below is an incomplete table of address modifiers: On the VME bus, all transfers are DMA and every card is a master or slave. In most bus standards, there

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792-421: The bus in two ways. With Release When Done (RWD), the master releases the bus when it completes a transfer and must re-arbitrate for the bus before every subsequent transfer. With Release On Request (ROR), the master retains the bus by continuing to assert BBSY* between transfers. ROR allows the master to retain control over the bus until a Bus Clear (BCLR*) is asserted by another master that wishes to arbitrate for

828-418: The bus. Thus a master that generates bursts of traffic can optimize its performance by arbitrating for the bus on only the first transfer of each burst. This decrease in transfer latency comes at the cost of somewhat higher transfer latency for other masters. Address modifiers are used to divide the VME bus address space into several distinct sub-spaces. The address modifier is a 6 bit wide set of signals on

864-495: The computer field, with various designs performing math even one bit at a time, known as "serial arithmetic", while most designs by the 1970s processed at least a few bits at a time. A common example is the Data General Nova, which was a 16-bit design that performed 16-bit math as a series of four 4-bit operations. 4-bits was the word size of a widely available single-chip ALU and thus allowed for inexpensive implementation. Using

900-516: The definition being applied to the 68000, the Nova would be a 4-bit computer, or 4/16. Not long after the introduction of the Nova, a second version was introduced, the SuperNova, which included four of the 4-bit ALUs running in parallel to perform math 16 bits at a time and therefore offer higher performance. This was invisible to the user and the programs, which always used 16-bit instructions and data. In

936-486: The first 24 address bits, 16 data bits and all of the control signals. P2 contains one more row, which includes the remaining 8 address bits and 16 data bits. A block transfer protocol allows several bus transfers to occur with a single address cycle. In block transfer mode, the first transfer includes an address cycle and subsequent transfers require only data cycles. The slave is responsible for ensuring that these transfers use successive addresses. Bus masters can release

972-712: The initial concept of VME64: multiplexing address and data lines (A64/D64) on the VMEbus. The concept was demonstrated the same year and placed in the VITA Technical Committee in 1990 as a performance enhancement to the VMEbus specification. In 1993, new activities began on the base-VME architecture, involving the implementation of high-speed serial and parallel sub-buses for use as I/O interconnections and data mover subsystems. These architectures can be used as message switches, routers and small multiprocessor parallel architectures. VITA's application for recognition as an accredited standards developer organization of ANSI

1008-469: The new VERSAbus. Sven Rau and Max Loesel of Motorola-Europe added a mechanical specification to the system, basing it on the Eurocard standard that was then late in the standardization process. The result was first known as VERSAbus-E but was later renamed to VMEbus , for VERSAmodule Eurocard bus (although some refer to it as Versa Module Europa ). At this point, a number of other companies involved in

1044-507: The three-chip Western Digital MCP-1600 (1975), and the five-chip Toshiba T-3412 (1976). Early single-chip 16-bit microprocessors ( c. 1975–76) include the Panafacom MN1610 (1975), National Semiconductor PACE (1975), General Instrument CP1600 (1975), Texas Instruments TMS9900 (1976), Ferranti F100-L , and the HP BPC . Other notable 16-bit processors include the Intel 8086 ,

1080-639: The upper 32 bits of an optional 64-bit PCI bus. 6U cards have an identical J1, a J2 that is always used for 64-bit PCI, as well as J3, J4, and J5 connectors for a variety of uses either as user-defined I/O or specified signaling such as Telephony and/or Ethernet signaling. Hot-plugging is a supported feature of CompactPCI. Some of the pins are slightly longer to provide proper grounding when devices are inserted and removed. The backplanes can be designed for 3.3 V VIO or 5 V VIO operation. These are differentiated by having 'Cadmium Yellow' coloured key for 3.3V or 'Brilliant Blue' colour for 5V operation. If

1116-475: Was also used to develop closely related standards, VXIbus and VPX . The VMEbus had a strong influence on many later computer buses such as STEbus . The architectural concepts of the VMEbus are based on VERSAbus, developed in the late 1970s by Motorola. This was later renamed "VME", short for Versa Module European, by Lyman (Lym) Hevle, then a VP with the Motorola Microsystems Operation. (He

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1152-524: Was called VME320. The VITA Standards Organization called for a new standard for unmodified VME32/64 backplanes. The new 2eSST protocol was approved in ANSI/VITA 1.5 in 1999. Over the years, many extensions have been added to the VME interface, providing 'sideband' channels of communication in parallel to VME itself. Some examples are IP Module, RACEway Interlink, SCSA, Gigabit Ethernet on VME64x Backplanes, PCI Express, RapidIO, StarFabric and InfiniBand. VMEbus

1188-520: Was formed under VITA under the direction of IEEE to create the first military, conduction-cooled 6U   × 160   mm, fully electrically and mechanically compatible, VMEbus board co-chaired by Dale Young (DY4 Systems) and Doug Patterson (Plessey Microsystems, then Radstone Technology). ANSI/IEEE-1101.2-1992 was later ratified and released in 1992 and remains in place as the conduction-cooled, international standard for all 6U VMEbus products. In 1989, John Peters of Performance Technologies Inc. developed

1224-561: Was granted in June 1993. Numerous other documents ( including mezzanine, P2 and serial bus standards) have been placed with VITA as the Public Domain Administrator of these technologies. In many ways the VMEbus is equivalent or analogous to the pins of the 68000 run out onto a backplane . However, one of the key features of the 68000 is a flat 32-bit memory model, free of memory segmentation and other "anti-features". The result

1260-584: Was later the founder of the VME Marketing Group, itself subsequently renamed to VME International Trade Association, or VITA). John Black of Motorola, Craig MacKenna of Mostek and Cecil Kaplinsky of Signetics developed the first draft of the VMEbus specification. In October 1981, at the System '81 trade show in Munich, West Germany, Motorola, Mostek, Signetics/Philips, and Thomson CSF announced their joint support of

1296-443: Was quite possibly the first-ever 16-bit computer. It was an unusual word size for the era; most systems used six-bit character code and used a word length of some multiple of 6-bits. This changed with the effort to introduce ASCII , which used a 7-bit code and naturally led to the use of an 8-bit multiple which could store a single ASCII character or two binary coded decimal digits. The 16-bit word length thus became more common in

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