Misplaced Pages

#946053

68-518: Cell , a shorthand for Cell Broadband Engine Architecture , is a 64-bit multi-core microprocessor and microarchitecture that combines a general-purpose PowerPC core of modest performance with streamlined coprocessing elements which greatly accelerate multimedia and vector processing applications, as well as many other forms of dedicated computation. It was developed by Sony , Toshiba , and IBM , an alliance known as "STI". The architectural design and first implementation were carried out at

136-522: A PCI Express accelerator board based on the PowerXCell 8i processor. Sony's high-performance media computing server ZEGO uses a 3.2 GHz Cell/B.E processor. The Cell Broadband Engine , or Cell as it is more commonly known, is a microprocessor intended as a hybrid of conventional desktop processors (such as the Athlon 64 , and Core 2 families) and more specialized high-performance processors, such as

204-496: A 90 nm process. An SPE can operate on sixteen 8-bit integers, eight 16-bit integers, four 32-bit integers, or four single-precision floating-point numbers in a single clock cycle, as well as a memory operation. Note that the SPU cannot directly access system memory; the 64-bit virtual memory addresses formed by the SPU must be passed from the SPU to the SPE memory flow controller (MFC) to set up

272-456: A DMA operation within the system address space. In one typical usage scenario, the system will load the SPEs with small programs (similar to threads ), chaining the SPEs together to handle each step in a complex operation. For instance, a set-top box might load programs for reading a DVD, video and audio decoding, and display and the data would be passed off from SPE to SPE until finally ending up on

340-449: A crossbar switch, and the way the bus is designed, you could actually pull out the EIB and put in a crossbar switch if you were willing to devote more silicon space on the chip to wiring. We had to find a balance between connectivity and area, and there just was not enough room to put a full crossbar switch in. So we came up with this ring structure which we think is very interesting. It fits within

408-418: A list of 2 to 2048 such blocks. One of the major design decisions in the architecture of Cell is the use of DMAs as a central means of intra-chip data transfer, with a view to enabling maximal asynchrony and concurrency in data processing inside a chip. The PPE, which is capable of running a conventional operating system, has control over the SPEs and can start, stop, interrupt, and schedule processes running on

476-595: A local memory of 256 KB. In total, the SPEs have 2 MB of local memory. The EIB is a communication bus internal to the Cell processor which connects the various on-chip system elements: the PPE processor, the memory controller (MIC), the eight SPE coprocessors, and two off-chip I/O interfaces, for a total of 12 participants in the PS3 (the number of SPU can vary in industrial applications). The EIB also includes an arbitration unit which functions as

544-452: A new op every three cycles. Each transfer always takes eight beats. That was one of the simplifications we made, it's optimized for streaming a lot of data. If you do small ops, it does not work quite as well. If you think of eight-car trains running around this track, as long as the trains aren't running into each other, they can coexist on the track. Each participant on the EIB has one 16-byte read port and one 16-byte write port. The limit for

612-438: A peak combined input speed of 25.6 GB/s and a peak combined output speed of 35 GB/s. To add further to the confusion, some older publications cite EIB bandwidth assuming a 4 GHz system clock. This reference frame results in an instantaneous EIB bandwidth figure of 384 GB/s and an arbitration-limited bandwidth figure of 256 GB/s. Multi-core processor Too Many Requests If you report this error to

680-498: A set of traffic lights. In some documents, IBM refers to EIB participants as 'units'. The EIB is presently implemented as a circular ring consisting of four 16-byte-wide unidirectional channels which counter-rotate in pairs. When traffic patterns permit, each channel can convey up to three transactions concurrently. As the EIB runs at half the system clock rate the effective channel rate is 16 bytes every two system clocks. At maximum concurrency , with three active transactions on each of

748-426: A single participant is to read and write at a rate of 16 bytes per EIB clock (for simplicity often regarded 8 bytes per system clock). Each SPU processor contains a dedicated DMA management queue capable of scheduling long sequences of transactions to various endpoints without interfering with the SPU's ongoing computations; these DMA queues can be managed locally or remotely as well, providing additional flexibility in

SECTION 10

#1732858676947

816-433: A total of 12,960 PowerXCell processors, with 12,960 PPE cores and 103,680 SPE cores, for a total of 116,640 cores. Logically, a TriBlade consists of two dual-core Opterons with 16 GB RAM and four PowerXCell 8i CPUs with 16 GB Cell RAM. Physically, a TriBlade consists of one LS21 Opteron blade , an expansion blade, and two QS22 Cell blades. The LS21 has two 1.8 GHz dual-core Opterons with 16 GB memory for

884-419: A variety of integer and floating-point formats. System memory addresses for both the PPE and SPE are expressed as 64-bit values for a theoretic address range of 2 bytes (16 exabytes or 16,777,216 terabytes). In practice, not all of these bits are implemented in hardware. Local store addresses internal to the SPU (Synergistic Processor Unit) processor are expressed as a 32-bit word. In documentation relating to Cell

952-550: A word is always taken to mean 32 bits, a doubleword means 64 bits, and a quadword means 128 bits. In 2008, IBM announced a revised variant of the Cell called the PowerXCell 8i , which is available in QS22 Blade Servers from IBM. The PowerXCell is manufactured on a 65 nm process, and adds support for up to 32 GB of slotted DDR2 memory, as well as dramatically improving double-precision floating-point performance on

1020-775: Is a common source of confusion. The PPE core is dual threaded and manifests in software as two independent threads of execution while each active SPE manifests as a single thread. In the PlayStation 3 configuration as described by Sony, the Cell processor provides nine independent threads of execution. On June 28, 2005, IBM and Mercury Computer Systems announced a partnership agreement to build Cell-based computer systems for embedded applications such as medical imaging , industrial inspection , aerospace and defense , seismic processing , and telecommunications . Mercury has since then released blades , conventional rack servers and PCI Express accelerator boards with Cell processors. In

1088-525: Is a heavy burden on the compiler). Each SPE has 6 execution units divided among odd and even pipelines on each SPE : The SPU runs a specially developed instruction set (ISA) with 128-bit SIMD organization for single and double precision instructions. With the current generation of the Cell, each SPE contains a 256  KiB embedded SRAM for instruction and data, called "Local Storage" (not to be mistaken for "Local Memory" in Sony's documents that refer to

1156-546: Is an IBM-designed and -fabricated PowerXCell 8i processor. As a supercomputer, the Roadrunner was considered an Opteron cluster with Cell accelerators, as each node consists of a Cell attached to an Opteron core and the Opterons to each other. Roadrunner was in development from 2002 and went online in 2006. Due to its novel design and complexity it was constructed in three phases and became fully operational in 2008. Its predecessor

1224-410: Is connected through twelve uplinks for each second-stage switch, which makes a total of 96 uplink connections. Overall system information: IBM Roadrunner was shut down on March 31, 2013. While the supercomputer was one of the fastest in the world, its energy efficiency was relatively low. Roadrunner delivered 444 megaflops per watt vs the 886 megaflops per watt of a comparable supercomputer. Before

1292-583: Is connected to the Opteron blade via HyperTransport. A Connected Unit is 60 BladeCenter H full of TriBlades, that is 180 TriBlades. All TriBlades are connected to a 288-port Voltaire ISR2012 Infiniband switch. Each CU also has access to the Panasas file system through twelve System x3755 servers. CU system information: The final cluster is made up of 18 connected units, which are connected via eight additional (second-stage) Infiniband ISR2012 switches. Each CU

1360-410: Is designed to compensate for this with compiler assistance, in which prepare-to-branch instructions are created. For double-precision floating-point operations, as sometimes used in personal computers and often used in scientific computing, Cell performance drops by an order of magnitude, but still reaches 20.8 GFLOPS (1.8 GFLOPS per SPE, 6.4 GFLOPS per PPE). The PowerXCell 8i variant, which

1428-501: Is the PowerPC based, dual-issue in-order two-way simultaneous-multithreaded CPU core with a 23-stage pipeline acting as the controller for the eight SPEs, which handle most of the computational workload. PPE has limited out of order execution capabilities; it can perform loads out of order and has delayed execution pipelines. The PPE will work with conventional operating systems due to its similarity to other 64-bit PowerPC processors, while

SECTION 20

#1732858676947

1496-523: The NVIDIA and ATI graphics-processors ( GPUs ). The longer name indicates its intended use, namely as a component in current and future online distribution systems; as such it may be utilized in high-definition displays and recording equipment, as well as HDTV systems. Additionally the processor may be suited to digital imaging systems (medical, scientific, etc. ) and physical simulation ( e.g. , scientific and structural engineering modeling). As used in

1564-544: The Open MPI Message Passing Interface implementation. Roadrunner occupied approximately 296 server racks which covered 560 square metres (6,000 sq ft) and became operational in 2008. It was decommissioned March 31, 2013. The DOE used the computer for simulating how nuclear materials age in order to predict whether the USA's aging arsenal of nuclear weapons are both safe and reliable. Other uses for

1632-452: The Pentium 4 and the Athlon 64 . However, comparing only floating-point abilities of a system is a one-dimensional and application-specific metric. Unlike a Cell processor, such desktop CPUs are more suited to the general-purpose software usually run on personal computers. In addition to executing multiple instructions per clock, processors from Intel and AMD feature branch predictors . The Cell

1700-535: The PowerXCell 8i , at the 65 nm feature size. In May 2008, an Opteron - and PowerXCell 8i-based supercomputer, the IBM Roadrunner system, became the world's first system to achieve one petaFLOPS, and was the fastest computer in the world until third quarter 2009. The world's three most energy-efficient supercomputers, as represented by the Green500 list, are similarly based on the PowerXCell 8i. In August 2009

1768-619: The 1 petaflops barrier during its fourth attempt on May 25, 2008. The complete system was moved to its permanent location in New Mexico in the summer of 2008. Roadrunner used two different models of processors. The first is the AMD Opteron 2210 , running at 1.8 GHz. Opterons are used both in the computational nodes feeding the Cells with useful data and in the system operations and communication nodes passing data between computing nodes and helping

1836-435: The 45 nm Cell processor was introduced in concert with Sony's PlayStation 3 Slim . By November 2009, IBM had discontinued the development of a Cell processor with 32 APUs but was still developing other Cell products. On May 17, 2005, Sony Computer Entertainment confirmed some specifications of the Cell processor that would be shipping in the then-forthcoming PlayStation 3 console. This Cell configuration has one PPE on

1904-554: The Broadband Engine was meant to have 1 teraFLOPS of raw computing power in theory. The design with 4 PPEs and 32 SPEs was never realized. Instead, Sony and IBM only manufactured a design with one PPE and 8 SPEs. This smaller design, the Cell Broadband Engine or Cell/BE was fabricated using a 90 nm SOI process. In March 2007, IBM announced that the 65 nm version of Cell/BE was in production at its plant (at

1972-580: The Broadband Engine was shown to be a chip package comprising four "Processing Elements", which was the patent's description for what is now known as the Power Processing Element (PPE). Each Processing Element would contain 8 "Synergistic Processing Elements" ( SPEs ) on the chip. This chip package was supposed to run at a clock speed of 4 GHz and with 32 SPEs providing 32  gigaFLOPS each SPE (FP32 Single precision), (Per SPU 4 Flops FPU + 4 Flops by integers Unit: 8 Flops per Cycle Per Spu),

2040-495: The Cell processor but during development, Microsoft approached IBM wanting a high-performance processor core for its Xbox 360 . IBM complied and made the tri-core Xenon processor , based on a slightly modified version of the PPE with added VMX128 extensions. Each SPE is a dual issue in order processor composed of a "Synergistic Processing Unit", SPU, and a "Memory Flow Controller", MFC ( DMA , MMU , and bus interface). SPEs do not have any branch prediction hardware (hence there

2108-568: The Cell. The Cell architecture includes a memory coherence architecture that emphasizes power efficiency, prioritizes bandwidth over low latency , and favors peak computational throughput over the simplicity of program code . For these reasons, Cell is widely regarded as a challenging environment for software development . IBM provided a Linux -based development platform to help developers program for Cell chips. In mid-2000, Sony Computer Entertainment , Toshiba Corporation , and IBM formed an alliance known as "STI" to design and manufacture

Cell (processor) - Misplaced Pages Continue

2176-562: The PPE, input/output elements and the SPEs, called the Element Interconnect Bus or EIB. To achieve the high performance needed for mathematically intensive tasks, such as decoding/encoding MPEG streams, generating or transforming three-dimensional data, or undertaking Fourier analysis of data, the Cell processor marries the SPEs and the PPE via EIB to give access, via fully cache coherent DMA (direct memory access) , to both main memory and to other external data storage. To make

2244-585: The PlayStation 3 it has 250 million transistors. In a simple analysis, the Cell processor can be split into four components: external input and output structures, the main processor called the Power Processing Element (PPE) (a two-way simultaneous-multithreaded PowerPC 2.02 core), eight fully functional co-processors called the Synergistic Processing Elements , or SPEs, and a specialized high-bandwidth circular data bus connecting

2312-563: The Roadrunner included the science, financial, automotive, and aerospace industries. Roadrunner differed from other contemporary supercomputers because it continued the hybrid approach to supercomputer design introduced by Seymour Cray in 1964 with the Control Data Corporation CDC 6600 and continued with the order of magnitude faster CDC 7600 in 1969. However, in this architecture the peripheral processors were used only for operating system functions and all applications ran in

2380-934: The SPEs are designed for vectorized floating point code execution. The PPE contains a 32 KiB level 1 instruction cache , a 32 KiB level 1 data cache, and a 512 KiB level 2 cache. The size of a cache line is 128 bytes in all caches. Additionally, IBM has included an AltiVec (VMX) unit which is fully pipelined for single precision floating point (Altivec 1 does not support double precision floating-point vectors.), 32-bit Fixed Point Unit (FXU) with 64-bit register file per thread, Load and Store Unit (LSU) , 64-bit Floating-Point Unit (FPU) , Branch Unit (BRU) and Branch Execution Unit(BXU). PPE consists of three main units: Instruction Unit (IU), Execution Unit (XU), and vector/scalar execution unit (VSU). IU contains L1 instruction cache, branch prediction hardware, instruction buffers, and dependency checking logic. XU contains integer execution units (FXU) and load-store unit (LSU). VSU contains all of

2448-486: The SPEs from a peak of about 12.8  GFLOPS to 102.4 GFLOPS total for eight SPEs, which, coincidentally, is the same peak performance as the NEC SX-9 vector processor released around the same time. The IBM Roadrunner supercomputer, the world's fastest during 2008–2009, consisted of 12,240 PowerXCell 8i processors, along with 6,562 AMD Opteron processors. The PowerXCell 8i powered super computers also dominated all of

2516-410: The SPEs or the PPE. Both the PPE and SPE are RISC architectures with a fixed-width 32-bit instruction format. The PPE contains a 64-bit general-purpose register set (GPR), a 64-bit floating-point register set (FPR), and a 128-bit Altivec register set. The SPE contains 128-bit registers only. These can be used for scalar data types ranging from 8-bits to 64-bits in size or for SIMD computations on

2584-411: The SPEs. To this end, the PPE has additional instructions relating to the control of the SPEs. Unlike SPEs, the PPE can read and write the main memory and the local memories of SPEs through the standard load/store instructions. Despite having Turing complete architectures, the SPEs are not fully autonomous and require the PPE to prime them before they can do any useful work. As most of the "horsepower" of

2652-622: The STI Design Center in Austin, Texas over a four-year period beginning March 2001 on a budget reported by Sony as approaching US$ 400 million. The first major commercial application of Cell was in Sony's PlayStation 3 game console , released in 2006. In May 2008, the Cell-based IBM Roadrunner supercomputer became the first TOP500 LINPACK sustained 1.0 petaflops system. Mercury Computer Systems also developed designs based on

2720-557: The TV. Another possibility is to partition the input data set and have several SPEs performing the same kind of operation in parallel. At 3.2 GHz, each SPE gives a theoretical 25.6 GFLOPS of single-precision performance. Compared to its personal computer contemporaries, the relatively high overall floating-point performance of a Cell processor seemingly dwarfs the abilities of the SIMD unit in CPUs like

2788-424: The U.S. Department of Energy's (DOE) National Nuclear Security Administration (NNSA). It was a hybrid design with 12,960 IBM PowerXCell 8i and 6,480 AMD Opteron dual-core processors in specially designed blade servers connected by InfiniBand . The Roadrunner used Red Hat Enterprise Linux along with Fedora as its operating systems, and was managed with xCAT distributed computing software. It also used

Cell (processor) - Misplaced Pages Continue

2856-450: The VRAM) which is visible to the PPE and can be addressed directly by software. Each SPE can support up to 4 GiB of local store memory. The local store does not operate like a conventional CPU cache since it is neither transparent to software nor does it contain hardware structures that predict which data to load. The SPEs contain a 128-bit, 128-entry register file and measures 14.5 mm on

2924-564: The Wikimedia System Administrators, please include the details below. Request from 172.68.168.151 via cp1112 cp1112, Varnish XID 390374259 Upstream caches: cp1112 int Error: 429, Too Many Requests at Fri, 29 Nov 2024 05:37:57 GMT IBM Roadrunner In November 2008, it reached a top performance of 1.456 petaFLOPS , retaining its top spot in the TOP500 list. It was also the fourth-most energy-efficient supercomputer in

2992-438: The area constraints and still has very impressive bandwidth. At 3.2 GHz, each channel flows at a rate of 25.6 GB/s. Viewing the EIB in isolation from the system elements it connects, achieving twelve concurrent transactions at this flow rate works out to an abstract EIB bandwidth of 307.2 GB/s. Based on this view many IBM publications depict available EIB bandwidth as "greater than 300 GB/s". This number reflects

3060-429: The best of EIB, and to overlap computation and data transfer, each of the nine processing elements (PPE and SPEs) is equipped with a DMA engine . Since the SPE's load/store instructions can only access its own local scratchpad memory , each SPE entirely depends on DMAs to transfer data to and from the main memory and other SPEs' local memories. A DMA operation can transfer either a single block area of size up to 16KB, or

3128-482: The chip layout had to be reworked, which resulted in both larger chip die and packaging. While the Cell chip can have a number of different configurations, the basic configuration is a multi-core chip composed of one "Power Processor Element" ("PPE") (sometimes called "Processing Element", or "PE"), and multiple "Synergistic Processing Elements" ("SPE"). The PPE and SPEs are linked together by an internal high speed bus dubbed "Element Interconnect Bus" ("EIB"). The PPE

3196-412: The circular configuration they adopted to spare resources rarely represents a limiting factor on the performance of the Cell chip as a whole. In the worst case, the programmer must take extra care to schedule communication patterns where the EIB is able to function at high concurrency levels. David Krolak explained: Well, in the beginning, early in the development process, several people were pushing for

3264-401: The control model. Data flows on an EIB channel stepwise around the ring. Since there are twelve participants, the total number of steps around the channel back to the point of origin is twelve. Six steps is the longest distance between any pair of participants. An EIB channel is not permitted to convey data requiring more than six steps; such data must take the shorter route around the circle in

3332-625: The core, with eight physical SPEs in silicon. In the PlayStation 3, one SPE is locked-out during the test process, a practice which helps to improve manufacturing yields, and another one is reserved for the OS, leaving 6 free SPEs to be used by games' code. The target clock-frequency at introduction is 3.2  GHz . The introductory design is fabricated using a 90 nm SOI process, with initial volume production slated for IBM's facility in East Fishkill, New York . The relationship between cores and threads

3400-447: The documentation set as yet made public by IBM. In practice, effective EIB bandwidth can also be limited by the ring participants involved. While each of the nine processing cores can sustain 25.6 GB/s read and write concurrently, the memory interface controller (MIC) is tied to a pair of XDR memory channels permitting a maximum flow of 25.6 GB/s for reads and writes combined and the two IO controllers are documented as supporting

3468-405: The execution resources for FPU and VMX. Each PPE can complete two double-precision operations per clock cycle using a scalar fused-multiply-add instruction, which translates to 6.4  GFLOPS at 3.2 GHz; or eight single-precision operations per clock cycle with a vector fused-multiply-add instruction, which translates to 25.6 GFLOPS at 3.2 GHz. The PPE was designed specifically for

SECTION 50

#1732858676947

3536-538: The fall of 2006, IBM released the QS20 blade module using double Cell BE processors for tremendous performance in certain applications, reaching a peak of 410 gigaFLOPS in Fp32 Single precision per module. The QS22 based on the PowerXCell 8i processor was used for the IBM Roadrunner supercomputer. Mercury and IBM uses the fully utilized Cell processor with eight active SPEs. On April 8, 2008, Fixstars Corporation released

3604-418: The feasibility to further construct and program the future hybrid version. This Phase 1 Roadrunner reached 71 teraflops and was in full operation at Los Alamos National Laboratory in 2006. Phase 2 known as AAIS (Advanced Architecture Initial System) included building a small hybrid version of the finished system using an older version of the Cell processor. This phase was used to build prototype applications for

3672-485: The four rings, the peak instantaneous EIB bandwidth is 96 bytes per clock (12 concurrent transactions × 16 bytes wide / 2 system clocks per transfer). While this figure is often quoted in IBM literature, it is unrealistic to simply scale this number by processor clock speed. The arbitration unit imposes additional constraints . IBM Senior Engineer David Krolak , EIB lead designer, explains the concurrency model: A ring can start

3740-500: The hybrid architecture. It went online in January 2007. The goal of Phase 3 was to reach sustained performance in excess of 1 petaflops. Additional Opteron nodes and new PowerXCell processors were added to the design. These PowerXCell processors are five times as powerful as the Cell processors used in Phase 2. It was built to full scale at IBM’s Poughkeepsie, New York facility, where it broke

3808-441: The one central processor. Most previous supercomputers had only used one processor architecture, since it was thought to be easier to design and program for. To realize the full potential of Roadrunner, all software had to be written specially for this hybrid architecture. The hybrid design consisted of dual-core Opteron server processors manufactured by AMD using the standard AMD64 architecture . Attached to each Opteron core

3876-533: The operators running the system. Roadrunner has a total of 6,912 Opteron processors with 6,480 used for computation and 432 for operation. The Opterons are connected together by HyperTransport links. Each Opteron has two cores for a total 13,824 cores. The second processor is the IBM PowerXCell 8i , running at 3.2 GHz. These processors have one general purpose core (PPE), and eight special performance cores (SPE) for floating point operations. Roadrunner has

3944-412: The other direction. The number of steps involved in sending the packet has very little impact on transfer latency: the clock speed driving the steps is very fast relative to other considerations. However, longer communication distances are detrimental to the overall performance of the EIB as they reduce available concurrency. Despite IBM's original desire to implement the EIB as a more powerful cross-bar,

4012-449: The peak instantaneous EIB bandwidth scaled by processor frequency. However, other technical restrictions are involved in the arbitration mechanism for packets accepted onto the bus. The IBM Systems Performance group explained: Each unit on the EIB can simultaneously send and receive 16 bytes of data every bus cycle. The maximum data bandwidth of the entire EIB is limited by the maximum rate at which addresses are snooped across all units in

4080-616: The processor. The STI Design Center opened in March 2001. The Cell was designed over a period of four years, using enhanced versions of the design tools for the POWER4 processor. Over 400 engineers from the three companies worked together in Austin, with critical support from eleven of IBM's design centers. During this period, IBM filed many patents pertaining to the Cell architecture, manufacturing process, and software environment. An early patent version of

4148-538: The system comes from the synergistic processing elements, the use of DMA as a method of data transfer and the limited local memory footprint of each SPE pose a major challenge to software developers who wish to make the most of this horsepower, demanding careful hand-tuning of programs to extract maximal performance from this CPU. The PPE and bus architecture includes various modes of operation giving different levels of memory protection , allowing areas of memory to be protected from access by specific processes running on

SECTION 60

#1732858676947

4216-469: The system, which is one per bus cycle. Since each snooped address request can potentially transfer up to 128 bytes, the theoretical peak data bandwidth on the EIB at 3.2 GHz is 128Bx1.6 GHz = 204.8 GB/s. This quote apparently represents the full extent of IBM's public disclosure of this mechanism and its impact. The EIB arbitration unit, the snooping mechanism, and interrupt generation on segment or page translation faults are not well described in

4284-461: The time, now GlobalFoundries') in East Fishkill, New York , with Bandai Namco Entertainment using the Cell/BE processor for their 357 arcade board as well as the subsequent 369. In February 2008, IBM announced that it would begin to fabricate Cell processors with the 45 nm process. In May 2008, IBM introduced the high-performance double-precision floating-point version of the Cell processor,

4352-610: The top 6 "greenest" systems in the Green500 list, with highest MFLOPS/Watt ratio supercomputers in the world. Beside the QS22 and supercomputers, the PowerXCell processor is also available as an accelerator on a PCI Express card and is used as the core processor in the QPACE project. Since the PowerXCell 8i removed the RAMBUS memory interface, and added significantly larger DDR2 interfaces and enhanced SPEs,

4420-517: The whole blade, providing 8GB for each CPU. Each QS22 has two PowerXCell 8i CPUs, running at 3.2 GHz and 8 GB memory, which makes 4 GB for each CPU. The expansion blade connects the two QS22 via four PCIe x8 links to the LS21, two links for each QS22. It also provides outside connectivity via an InfiniBand 4x DDR adapter. This makes a total width of four slots for a single TriBlade. Three TriBlades fit into one BladeCenter H chassis. The expansion blade

4488-462: The world on the Supermicro Green500 list, with an operational rate of 444.94 megaflops per watt of power used. The hybrid Roadrunner design was then reused for several other energy efficient supercomputers. Roadrunner was decommissioned by Los Alamos on March 31, 2013. In its place, Los Alamos commissioned a supercomputer called Cielo , which was installed in 2010. IBM built the computer for

4556-409: Was a machine also developed at Los Alamos named Dark Horse. This machine was one of the earliest hybrid architecture systems originally based on ARM and then moved to the Cell processor. It was entirely a 3D design, its design integrated 3D memory, networking, processors and a number of other technologies. The first phase of the Roadrunner was building a standard Opteron based cluster, while evaluating

4624-482: Was specifically designed for double-precision, reaches 102.4 GFLOPS in double-precision calculations. Tests by IBM show that the SPEs can reach 98% of their theoretical peak performance running optimized parallel matrix multiplication. Toshiba has developed a co-processor powered by four SPEs, but no PPE, called the SpursEngine designed to accelerate 3D and movie effects in consumer electronics. Each SPE has

#946053