The POWER4 is a microprocessor developed by International Business Machines (IBM) that implemented the 64-bit PowerPC and PowerPC AS instruction set architectures . Released in 2001, the POWER4 succeeded the POWER3 and RS64 microprocessors, enabling RS/6000 and eServer iSeries models of AS/400 computer servers to run on the same processor, as a step toward converging the two lines. The POWER4 was a multicore microprocessor, with two cores on a single die, the first non-embedded microprocessor to do so. POWER4 Chip was first commercially available multiprocessor chip. The original POWER4 had a clock speed of 1.1 and 1.3 GHz, while an enhanced version, the POWER4+, reached a clock speed of 1.9 GHz. The PowerPC 970 is a derivative of the POWER4.
9-426: The POWER4 has a unified L2 cache, divided into three equal parts. Each has its own independent L2 controller which can feed 32 bytes of data per cycle. The Core Interface Unit (CIU) connects each L2 controller to either the data cache or instruction cache in either of the two processors. The Non-Cacheable (NC) Unit is responsible for handling instruction serializing functions and performing any noncacheable operations in
18-469: A branch unit (BR), and a conditional-register unit (CR). These execution units can complete up to eight operations per clock (not including the BR and CR units): The pipeline stages are: The POWER4 also came in a configuration using a multi-chip module (MCM) containing four POWER4 dies in a single package, with up to 128 MB of shared L3 ECC cache per MCM. The POWER4+, released in 2003, was an improved version of
27-408: Is provided. There is also a Built In Self Test function (BIST) and Performance Monitoring Unit (PMU). Power-on reset (POR) is supported. The POWER4 implements a superscalar microarchitecture through high-frequency speculative out-of-order execution using eight independent execution units. They are: two floating-point units (FP1-2), two load-store units (LD1-2), two fixed-point units (FX1-2),
36-449: Is reached. One of the issues with using an RC network to generate a PoR pulse is the sensitivity of the R and C values to the power-supply ramp characteristics. When the power supply ramp is rapid, the R and C values can be calculated so that the time to reach the switching threshold of the Schmitt trigger is enough to apply a long enough reset pulse. When the power-supply ramp itself is slow,
45-461: The POWER4 that ran at up to 1.9 GHz. It contained 184 million transistors, measured 267 mm, and was fabricated in a 0.13 Ξm SOI CMOS process with eight layers of copper interconnect. Power-on reset A power-on reset ( PoR , POR ) generator is a microcontroller or microprocessor peripheral that generates a reset signal when power is applied to the device . It ensures that
54-520: The RC network tends to get charged up along with the power-supply ramp up. So when the input Schmitt stage is all powered up and ready, the input voltage from the RC network would already have crossed the Schmitt trigger point. This means that there might not be a reset pulse supplied to the core of the VLSI. On an IBM mainframe, a power-on reset ( POR ) is a sequence of actions that the processor performs either due to
63-412: The device starts operating in a known state . In VLSI devices, the power-on reset ( PoR ) is an electronic device incorporated into the integrated circuit that detects the power applied to the chip and generates a reset impulse that goes to the entire circuit placing it into a known state. A simple PoR uses the charging of a capacitor, in series with a resistor, to measure a time period during which
72-447: The rest of the circuit is held in a reset state. A Schmitt trigger may be used to deassert the reset signal cleanly, once the rising voltage of the RC network passes the threshold voltage of the Schmitt trigger. The resistor and capacitor values should be determined so that the charging of the RC network takes long enough that the supply voltage will have stabilised by the time the threshold
81-492: The storage topology. There is an L3 cache controller, but the actual memory is off-chip. The GX bus controller controls I/O device communications, and there are two 4-byte wide GX buses, one incoming and the other outgoing. The Fabric Controller is the master controller for the network of buses, controlling communications for both L1/L2 controllers, communications between POWER4 chips {4-way, 8-way, 16-way, 32-way} and POWER4 MCM's. Trace-and-Debug, used for First Failure Data Capture,
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