TLCS is a prefix applied to microcontrollers made by Toshiba . The product line includes multiple families of CISC and RISC architectures. Individual components generally have a part number beginning with "TMP". E.g. the TMP8048AP is a member of the TLCS-48 family.
16-623: The TLCS-12 was a 12-bit microprocessor and central processing unit manufactured by Toshiba. It began development in 1971, and was completed in 1973. It was a 32 mm MOS integrated circuit chip with about 2,800 silicon gates , fabricated on a 6 Ξm process with NMOS logic . It was used in the Ford EEC engine control unit system, which began production in 1974 and went into mass production in 1975. The system memory included 512-bit RAM , 2 kb ROM and 2 kb EPROM . The TLCS-12A [ jp ] , an improved version of
32-402: A 12-bit resolution. Some PIC microcontrollers use a 12-bit word size. 12 binary digits, or 3 nibbles (a 'tribble'), have 4096 (10000 octal , 1000 hexadecimal ) distinct combinations. Hence, a microprocessor with 12-bit memory addresses can directly access 4096 words (4 kW) of word-addressable memory. IBM System/360 instruction formats use a 12-bit displacement field which, added to
48-807: Is available for free. The free Small Device C Compiler supports the TLCS-90. There is a project for porting GNU assembler to the TLCS-900 family. Alfred Arnold's The Macroassembler AS [1] is a free assembler supporting the TLCS-47, TLCS-870, TLCS-90, TLCS-900 and TLCS-9000 families. 12-bit computing In computer architecture , 12-bit integers , memory addresses , or other data units are those that are 12 bits (1.5 octets) wide. Also, 12-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers , address buses , or data buses of that size. Before
64-449: Is unusual in that the prefix specifies one operand of the extended instruction, and unlike the single-byte prefixes used by the Z80 or x86 architecture, may itself be followed by operand bytes. After the prefix bytes, the second opcode byte specifies the operation and second operand. For example, the instruction ADD (IX+127),5 is encoded as F4 7F 68 05 , where the first two bytes specify
80-536: The Z80 . These are no longer advertised on the Toshiba website. The TLCS-90 inherits most Z80 features, such as: There are, however, significant differences. It omits the separate I/O address space of the Z80, but adds more flexibility to operand combinations, some new operations (notably multiply and divide), and several additional addressing modes : Most of the functionality of 8-bit accumulator A has also been implemented for
96-492: The 16-bit HL register pair, such as the missing SUB and CP instructions, and the AND , XOR , and OR bitwise instructions. The ADD HL,rr flag quirk from the Z80 is implemented. Furthermore, the DJNZ BC,addr instruction was added to ease 16-bit loop counting. TLCS-90 SoC packages include the 4-bit BX and BY registers, which get concatenated with effective addresses based on
112-469: The 16-bit register SR) has an alternate register called F'. Executing EX AF,AF' from the TLCS-90 requires executing both EX A,A' and EX F,F' . The TLCS-900 also includes 4 "microDMA" transfer channels, each of which have programmable source and destination addresses, transfer counts, data sizes (byte, word, and longword), and various transfer modes. These are triggered the same way as normal interrupts, and interrupt program execution upon
128-613: The IX or IY register, allowing the processor to address up to one megabyte of memory. The processor includes the INCX ($ FF00+n) and DECX ($ FF00+n) instructions, which are useful for performing 20-bit pointer arithmetic using the IX and BX registers or the IY and BY registers. Instructions are divided into one-byte basic and two-byte extended instructions. Opcodes E0 16 through FE 16 are prefixes which begin an extended instruction. The instruction encoding
144-503: The TLCS-12, was announced in 1975. The microcontrollers in the TLCS-47 category are 4-bit systems. These are no longer advertised on the Toshiba website. The TLCS-48 family were clones of the Intel MCS-48 (8048) microcontroller. These were a series of Zilog Z80 compatible microcontrollers. The microcontrollers in the TLCS-90 family use a 8-bit / 16-bit architecture reminiscent of
160-581: The TLCS-90 architecture, and includes 32-bit registers and a 24-bit address bus. Most implementations (TLCS-900, TLCS-900/L, TLCS-900/H and TLCS-900/L1 series) have 16-bit internal data paths, like the MC68000 , while the TLCS-900/H1 series is 32 bits wide internally (like the MC68020 ). The instruction set is mostly upward-compatible with the TLCS-90, although the binary encoding differs. The same scheme of encoding
176-456: The addressing mode before the instruction's opcode and additional operands is implemented. The early models supported both a "minimum mode" where the banked registers and program counter were 16 bits wide, and a "maximum mode" which had all 32-bit general purpose registers. Later models omitted the minimum mode. In maximum mode, there are 4 banks of four 32-bit registers, each of which can be split into two 16-bit halves or four 8-bit quarters. In
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#1732858994434192-511: The destination address, the third byte specifies the operation, and the fourth byte provides the source operand. The microcontrollers in the TLCS-870 family (TLCS-870, TLCS-870/X, TLCS-870/C and TLCS-870/C1 series) use a 8-bit / 16-bit architecture inspired by the TLCS-90, but less like the Z80. The TLCS-870 is the original, with a 16-bit address space, which was extended in two different directions: The TLCS-900 family inherits most features from
208-475: The minimum mode of early models, there are 8 banks of four 16-bit registers, which can be split into 8-bit halves. The processor can use the current bank (pointed to by the RFP field in the 16-bit status register SR), the previous bank to be compatible with the alternate register scheme of the TLCS-90, or any arbitrary bank number from 0 to 7. There is also a fixed set of four 32-bit registers, with one of them dedicated as
224-428: The stack pointer. Early models had two separate stack pointers for user and system modes. Normally, only a set of 8 registers can be addressed from a 3-bit code; addressing all registers requires an additional 6/8-bit code byte that can only be inserted in the prefixed addressing mode operand, restricting which combinations of registers can be used for the source and destination operands. The F register (low 8-bit half of
240-560: The transferring process. The TLCS-900/H model was most prominently used in the Neo Geo Pocket and Neo Geo Pocket Color . Current TLCS processors offer some or all of the following features: As demand for these features differs widely depending on the requirements for a specific project (low energy consumption; high number of I/O ports; etc.), customers can choose from a wide range of different versions. Toshiba offers an ANSI C compatible C compiler and an assembler . Neither tool
256-560: The widespread adoption of ASCII in the late 1960s, six-bit character codes were common and a 12-bit word, which could hold two characters, was a convenient size. This also made it useful for storing a single decimal digit along with a sign. Possibly the best-known 12-bit CPU is the PDP-8 and its relatives, such as the Intersil 6100 microprocessor produced in various forms from August 1963 to mid-1990. Many analog to digital converters (ADCs) have
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