Sun Blade is a line of blade server computer systems sold by Sun Microsystems from 2006 onwards.
54-545: In June 2006, Sun announced the AMD Opteron -based Sun Blade 8000 modular blade server system. The Sun Blade 8000 chassis can hold up to 10 Sun Blade X8420 or X8440 modules. In July 2007, Sun launched the Sun Blade 6000 Modular System. This allowed up to 10 mixed UltraSPARC and x64 architecture blades. The Sun Blade T6300 and T6320 modules run Solaris and use UltraSPARC T1 and UltraSPARC T2 processors respectively, while
108-715: A HyperTransport 3.1 link connecting the two dies. These CPUs updated the multi-socket Opteron platform to use DDR3 memory and increased the maximum HyperTransport link speed from 2.40 GHz (4.80 GT/s) for the Istanbul CPUs to 3.20 GHz (6.40 GT/s). AMD changed the naming scheme for its Opteron models. Opteron 4000 series CPUs on Socket C32 (released July 2010) are dual-socket capable and are targeted at uniprocessor and dual-processor uses. The Opteron 6000 series CPUs on Socket G34 are quad-socket capable and are targeted at high-end dual-processor and quad-processor applications. AMD released Socket 939 Opterons, reducing
162-429: A multiprocessor computer hardware and software architecture where two or more identical processors are connected to a single, shared main memory , have full access to all input and output devices, and are controlled by a single operating system instance that treats all processors equally, reserving none for special purposes. Most multiprocessor systems today use an SMP architecture. In the case of multi-core processors ,
216-596: A 45 nm manufacturing process and are similar to the Deneb -based Phenom II X4 CPUs. The Socket AM3 quad-core Opterons are code-named "Suzuka". These CPUs carry model numbers of 1381 (2.50 GHz), 1385 (2.70 GHz), and 1389 (2.90 GHz). Socket AM3+ was introduced in 2011 and is a modification of AM3 for the Bulldozer microarchitecture. Opteron CPUs in the AM3+ package are named Opteron 3xxx. Socket F ( LGA 1207 contacts)
270-432: A NUMA architecture, processors may access local memory quickly and remote memory more slowly. This can dramatically improve memory throughput as long as the data are localized to specific processes (and thus processors). On the downside, NUMA makes the cost of moving data from one processor to another, as in workload balancing, more expensive. The benefits of NUMA are limited to particular workloads, notably on servers where
324-514: A few limits on the scalability of SMP due to cache coherence and shared objects. Uniprocessor and SMP systems require different programming methods to achieve maximum performance. Programs running on SMP systems may experience an increase in performance even when they have been written for uniprocessor systems. This is because hardware interrupts usually suspends program execution while the kernel that handles them can execute on an idle processor instead. The effect in most applications (e.g. games)
378-969: A lower TDP than a standard Opteron. The suffix SE indicates a top-of-the-line model having a higher TDP than a standard Opteron. Starting from 65 nm fabrication process, the Opteron codenames have been based on Formula 1 hosting cities; AMD has a long term sponsorship with F1's most successful team, Ferrari . Released June 1, 2009. Released March 29, 2010. Released March 29, 2010 Released June 23, 2010 Released June 23, 2010 Released March 20, 2012. Released March 20, 2012. Released November 14, 2011. Released November 14, 2011. Released November 14, 2011. Released November 14, 2011. Released November 14, 2011. Released November 14, 2011. Released December 4, 2012. Released December 4, 2012. Released December 4, 2012 Released December 4, 2012 Symmetric multiprocessing Symmetric multiprocessing or shared-memory multiprocessing ( SMP ) involves
432-498: A memory architecture similar to the Opteron's for the Intel Core i7 family of processors and their Xeon derivatives. In April 2005, AMD introduced its first multi-core Opterons. At the time, AMD's use of the term multi-core in practice meant dual-core ; each physical Opteron chip contained two processor cores. This effectively doubled the computing performance available to each motherboard processor socket. One socket could then deliver
486-580: A pool of homogeneous processors running independently of each other. Each processor, executing different programs and working on different sets of data, has the capability of sharing common resources (memory, I/O device, interrupt system and so on) that are connected using a system bus or a crossbar . SMP systems have centralized shared memory called main memory (MM) operating under a single operating system with two or more homogeneous processors. Usually each processor has an associated private high-speed memory known as cache memory (or cache) to speed up
540-571: A quad-core device, called the Companion core, built specifically for executing tasks at a lower frequency during mobile active standby mode, video playback, and music playback. Project Kal-El ( Tegra 3 ), patented by NVIDIA, was the first SoC (System on Chip) to implement this new vSMP technology. This technology not only reduces mobile power consumption during active standby state, but also maximizes quad core performance during active usage for intensive mobile applications. Overall this technology addresses
594-459: A small write-through cache connected to a common memory to form a shared memory system. Another early commercial Unix SMP implementation was the NUMA based Honeywell Information Systems Italy XPS-100 designed by Dan Gielan of VAST Corporation in 1985. Its design supported up to 14 processors, but due to electrical limitations, the largest marketed version was a dual processor system. The operating system
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#1732852043833648-678: A system with more than one process running can run different processes on different processors. On personal computers , SMP is less useful for applications that have not been modified. If the system rarely runs more than one process at a time, SMP is useful only for applications that have been modified for multithreaded (multitasked) processing. Custom-programmed software can be written or modified to use multiple threads, so that it can make use of multiple processors. Multithreaded programs can also be used in time-sharing and server systems that support multithreading, allowing them to make more use of multiple processors. In current SMP systems, all of
702-409: A uniprocessor system, because different programs can run on different CPUs simultaneously. Conversely, asymmetric multiprocessing (AMP) usually allows only one processor to run a program or task at a time. For example, AMP can be used in assigning specific tasks to CPU based to priority and importance of task completion. AMP was created well before SMP in terms of handling multiple CPUs, which explains
756-436: A uniprocessor system. SMP systems can also lead to more complexity regarding instruction sets. A homogeneous processor system typically requires extra registers for "special instructions" such as SIMD (MMX, SSE, etc.), while a heterogeneous system can implement different types of hardware for different instructions/uses. When more than one program executes at the same time, an SMP system has considerably better performance than
810-502: A variety of computing benchmarks, the Opteron architecture has demonstrated better multi-processor scaling than the Intel Xeon which did not have a point to point system until QPI and integrated memory controllers with the Nehalem design. This is primarily because adding another Opteron processor increases memory bandwidth, while that is not always the case for Xeon systems, and the fact that
864-490: Is AMD’s second generation of Opteron socket. This socket supports processors such as the Santa Rosa, Barcelona, Shanghai, and Istanbul codenamed processors. the "lidded land grid array " socket adds support for DDR2 SDRAM and improved HyperTransport version 3 connectivity. Physically the socket and processor package are nearly identical, although not generally compatible with socket 1207 FX . Socket G34 (LGA 1944 contacts)
918-532: Is a stub . You can help Misplaced Pages by expanding it . AMD Opteron Opteron is AMD 's x86 former server and workstation processor line, and was the first processor which supported the AMD64 instruction set architecture (known generically as x86-64 ). It was released on April 22, 2003, with the SledgeHammer core (K8) and was intended to compete in the server and workstation markets, particularly in
972-399: Is handled independently, this creates an embarrassingly parallel situation across the entire multi-compilation-unit project, allowing near linear scaling of compilation time. Distributed computing projects are inherently parallel by design.) Systems programmers must build support for SMP into the operating system , otherwise, the additional processors remain idle and the system functions as
1026-407: Is intended by SMP is a shared memory multiprocessor where the cost of accessing a memory location is the same for all processors; that is, it has uniform access costs when the access actually is to memory. If the location is cached, the access will be faster, but cache access times and memory access times are the same on all processors." SMP systems are tightly coupled multiprocessor systems with
1080-544: Is less noteworthy, as major RISC architectures (such as SPARC , Alpha , PA-RISC , PowerPC , MIPS ) have been 64-bit for many years. In combining these two capabilities, however, the Opteron earned recognition for its ability to run the vast installed base of x86 applications economically, while simultaneously offering an upgrade path to 64-bit computing . The Opteron processor possesses an integrated memory controller supporting DDR SDRAM , DDR2 SDRAM or DDR3 SDRAM (depending on processor generation). This both reduces
1134-411: Is not so much a performance increase as the appearance that the program is running much more smoothly. Some applications, particularly building software and some distributed computing projects, run faster by a factor of (nearly) the number of additional processors. (Compilers by themselves are single threaded, but, when building a software project with multiple compilation units, if each compilation unit
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#17328520438331188-424: Is not the same as standard symmetric multiprocessing ; instead of having one bank of memory for all CPUs, each CPU has its own memory. Thus the Opteron is a Non-Uniform Memory Access (NUMA) architecture. The Opteron CPU directly supports up to an 8-way configuration, which can be found in mid-level servers. Enterprise-level servers use additional (and expensive) routing chips to support more than 8 CPUs per box. In
1242-425: Is one of the third generation of Opteron sockets, along with Socket C32 . This socket supports Magny-Cours Opteron 6100, Bulldozer-based Interlagos Opteron 6200, and Piledriver-based "Abu Dhabi" Opteron 6300 series processors. This socket supports four channels of DDR3 SDRAM (two per CPU die). Unlike previous multi-CPU Opteron sockets, Socket G34 CPUs will function with unbuffered ECC or non-ECC RAM in addition to
1296-503: Is serialized; this and cache coherency issues cause performance to lag slightly behind the number of additional processors in the system. SMP uses a single shared system bus that represents one of the earliest styles of multiprocessor machine architectures, typically used for building smaller computers with up to 8 processors. Larger computer systems might use newer architectures such as NUMA (Non-Uniform Memory Access), which dedicates different memory banks to different processors. In
1350-753: The Michigan Terminal System (MTS), used both CPUs. Both processors could access data channels and initiate I/O. In OS/360 M65MP, peripherals could generally be attached to either processor since the operating system kernel ran on both processors (though with a "big lock" around the I/O handler). The MTS supervisor (UMMPS) has the ability to run on both CPUs of the IBM System/360 model 67–2. Supervisor locks were small and used to protect individual common data structures that might be accessed simultaneously from either CPU. Other mainframes that supported SMP included
1404-554: The UNIVAC 1108 II , released in 1965, which supported up to three CPUs, and the GE-635 and GE-645 , although GECOS on multiprocessor GE-635 systems ran in a master-slave asymmetric fashion, unlike Multics on multiprocessor GE-645 systems, which ran in a symmetric fashion. Starting with its version 7.0 (1972), Digital Equipment Corporation 's operating system TOPS-10 implemented the SMP feature,
1458-553: The 8000 Series (quad or octo socket-capable). The 1000 Series uses the AM2 socket . The 2000 Series and 8000 Series use Socket F . [1] AMD announced its third-generation quad-core Opteron chips on September 10, 2007 with hardware vendors announcing servers in the following month. Based on a core design codenamed Barcelona , new power and thermal management techniques were planned for the chips. Earlier dual core DDR2 based platforms were upgradeable to quad core chips. The fourth generation
1512-555: The Opterons use a switched fabric , rather than a shared bus . In particular, the Opteron's integrated memory controller allows the CPU to access local RAM very quickly. In contrast, multiprocessor Xeon system CPUs share only two common buses for both processor-processor and processor-memory communication. As the number of CPUs increases in a typical Xeon system, contention for the shared bus causes computing efficiency to drop. Intel migrated to
1566-402: The SMP architecture applies to the cores, treating them as separate processors. Professor John D. Kubiatowicz considers traditionally SMP systems to contain processors without caches. Culler and Pal-Singh in their 1998 book "Parallel Computer Architecture: A Hardware/Software Approach" mention: "The term SMP is widely used but causes a bit of confusion. [...] The more precise description of what
1620-457: The Sun Blade X6220 and X6250 modules use AMD Opteron or Intel Xeon 5000-series processors respectively. In November 2007, Sun announced the Sun Blade 6048 Modular System, supporting up to 48 UltraSPARC, AMD Opteron and/or Intel Xeon blades. The X-series blades support Solaris , Oracle Linux , RHEL , SLES , Windows Server or VMware . This computer server-related article
1674-653: The cost of motherboards for low-end servers and workstations. Except for the fact they have 1 MB L2 cache (versus 512 KB for the Athlon 64) the Socket 939 Opterons are identical to the San Diego and Toledo core Athlon 64s , but are run at lower clock speeds than the cores are capable of, making them more stable. Socket AM2 Opterons are available for servers that only have a single-chip setup. Codenamed Santa Ana, rev. F dual core AM2 Opterons feature 2 × 1 MB L2 cache, unlike
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1728-441: The data are often associated strongly with certain tasks or users. Finally, there is computer clustered multiprocessing (such as Beowulf ), in which not all memory is available to all processors. Clustering techniques are used fairly extensively to build very large supercomputers. Variable Symmetric Multiprocessing (vSMP) is a specific mobile use case technology initiated by NVIDIA. This technology includes an extra fifth core in
1782-488: The data for that task is located in memory, provided that each task in the system is not in execution on two or more processors at the same time. With proper operating system support, SMP systems can easily move tasks between processors to balance the workload efficiently. The earliest production system with multiple identical processors was the Burroughs B5000 , which was functional around 1961. However at run-time this
1836-712: The earliest system running SMP was the DECSystem 1077 dual KI10 processor system. Later KL10 system could aggregate up to 8 CPUs in a SMP manner. In contrast, DECs first multi-processor VAX system, the VAX-11/782, was asymmetric, but later VAX multiprocessor systems were SMP. Early commercial Unix SMP implementations included the Sequent Computer Systems Balance 8000 (released in 1984) and Balance 21000 (released in 1986). Both models were based on 10 MHz National Semiconductor NS32032 processors, each with
1890-453: The form Opteron XZYY . For all first, second, and third-generation Opterons, the first digit (the X ) specifies the number of CPUs on the target machine: For Socket F and Socket AM2 Opterons, the second digit (the Z ) represents the processor generation. Presently, only 2 (dual-core, DDR2), 3 (quad-core, DDR2) and 4 (six-core, DDR2) are used. Socket C32 and G34 Opterons use a new four-digit numbering scheme. The first digit refers to
1944-472: The implementation of the AMD K10 microarchitecture. New processors, launched in the third quarter of 2007 (codename Barcelona ), incorporate a variety of improvements, particularly in memory prefetching, speculative loads, SIMD execution and branch prediction , yielding an appreciable performance improvement over K8-based Opterons, within the same power envelope. In 2007 AMD introduced a scheme to characterize
1998-510: The lack of performance based on the example provided. In cases where an SMP environment processes many jobs, administrators often experience a loss of hardware efficiency. Software programs have been developed to schedule jobs and other functions of the computer so that the processor utilization reaches its maximum potential. Good software packages can achieve this maximum potential by scheduling each CPU separately, as well as being able to integrate multiple SMP machines and clusters. Access to RAM
2052-489: The last two digits in the model number (the YY ) indicate the clock frequency of a CPU, a higher number indicating a higher clock frequency. This speed indication is comparable to processors of the same generation if they have the same amount of cores, single-cores and dual-cores have different indications despite sometimes having the same clock frequency. The suffix HE or EE indicates a high-efficiency/energy-efficiency model having
2106-580: The latency penalty for accessing the main RAM and eliminates the need for a separate northbridge chip. In multi-processor systems (more than one Opteron on a single motherboard ), the CPUs communicate using the Direct Connect Architecture over high-speed HyperTransport links. Each CPU can access the main memory of another processor, transparent to the programmer. The Opteron approach to multi-processing
2160-473: The main memory data access and to reduce the system bus traffic. Processors may be interconnected using buses, crossbar switches or on-chip mesh networks. The bottleneck in the scalability of SMP using buses or crossbar switches is the bandwidth and power consumption of the interconnect among the various processors, the memory, and the disk arrays. Mesh architectures avoid these bottlenecks, and provide nearly linear scalability to much higher processor counts at
2214-703: The majority of their Athlon 64 X2 cousins which feature 2 × 512 KB L2 cache. These CPUs are given model numbers ranging from 1210 to 1224. AMD introduced three quad-core Opterons on Socket AM2+ for single-CPU servers in 2007. These CPUs are produced on a 65 nm manufacturing process and are similar to the Agena Phenom X4 CPUs. The Socket AM2+ quad-core Opterons are code-named "Budapest". The Socket AM2+ Opterons carry model numbers of 1352 (2.10 GHz), 1354 (2.20 GHz), and 1356 (2.30 GHz). AMD introduced three quad-core Opterons on Socket AM3 for single-CPU servers in 2009. These CPUs are produced on
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2268-556: The need for increase in battery life performance during active and standby usage by reducing the power consumption in mobile processors. Unlike current SMP architectures, the vSMP Companion core is OS transparent meaning that the operating system and the running applications are totally unaware of this extra core but are still able to take advantage of it. Some of the advantages of the vSMP architecture includes cache coherency, OS efficiency, and power optimization. The advantages for this architecture are explained below: These advantages lead
2322-466: The number of CPUs in the target machine: Like the previous second and third generation Opterons, the second number refers to the processor generation. "1" refers to AMD K10-based units ( Magny-Cours and Lisbon ), "2" refers to the Bulldozer -based Interlagos , Valencia , and Zurich -based units, and "3" refers to the Piledriver -based Abu Dhabi , Seoul , and Delhi -based units. For all Opterons,
2376-420: The performance of two processors, two sockets could deliver the performance of four processors, and so on. Because motherboard costs increase dramatically as the number of CPU sockets increase, multicore CPUs enable a multiprocessing system to be built at lower cost. AMD's model number scheme has changed somewhat in light of its new multicore lineup. At the time of its introduction, AMD's fastest multicore Opteron
2430-459: The power consumption of new processors under "average" daily usage, named average CPU power (ACP). The Opteron X1150 and Opteron X2150 APU are used with the BGA-769 or Socket FT3 . See APU features table For Socket 940 and Socket 939 Opterons, each chip has a three-digit model number, in the form Opteron XYY . For Socket F and Socket AM2 Opterons, each chip has a four-digit model number, in
2484-615: The processors are tightly coupled inside the same box with a bus or switch; on earlier SMP systems, a single CPU took an entire cabinet. Some of the components that are shared are global memory, disks, and I/O devices. Only one copy of an OS runs on all the processors, and the OS must be designed to take advantage of this architecture. Some of the basic advantages involves cost-effective ways to increase throughput. To solve different problems and tasks, SMP applies multiple processors to that one problem, known as parallel programming . However, there are
2538-526: The sacrifice of programmability: Serious programming challenges remain with this kind of architecture because it requires two distinct modes of programming; one for the CPUs themselves and one for the interconnect between the CPUs. A single programming language would have to be able to not only partition the workload, but also comprehend the memory locality, which is severe in a mesh-based architecture. SMP systems allow any processor to work on any task no matter where
2592-416: The same segment as the Intel Xeon processor. Processors based on the AMD K10 microarchitecture (codenamed Barcelona ) were announced on September 10, 2007, featuring a new quad-core configuration. The last released Opteron CPUs are the Piledriver -based Opteron 4300 and 6300 series processors, codenamed "Seoul" and "Abu Dhabi" respectively. In January 2016, the first ARMv8-A based Opteron-branded SoC
2646-512: The traditional registered ECC RAM. Socket C32 (LGA 1207 contacts) is the other member of the third generation of Opteron sockets. This socket is physically similar to Socket F but is not compatible with Socket F CPUs. Socket C32 uses DDR3 SDRAM and is keyed differently so as to prevent the insertion of Socket F CPUs that can use only DDR2 SDRAM. Like Socket G34, Socket C32 CPUs will be able to use unbuffered ECC or non-ECC RAM in addition to registered ECC SDRAM. The Opteron line saw an update with
2700-477: Was asymmetric , with one processor restricted to application programs while the other processor mainly handled the operating system and hardware interrupts. The Burroughs D825 first implemented SMP in 1962. IBM offered dual-processor computer systems based on its System/360 Model 65 and the closely related Model 67 and 67–2. The operating systems that ran on these machines were OS/360 M65MP and TSS/360 . Other software developed at universities, notably
2754-585: Was announced in June 2009 with the Istanbul hexa-cores. It introduced HT Assist , an additional directory for data location, reducing the overhead for probing and broadcasts. HT Assist uses 1 MB L3 cache per CPU when activated. In March 2010 AMD released the Magny-Cours Opteron 6100 series CPUs for Socket G34 . These are 8- and 12-core multi-chip module CPUs consisting of two four or six-core dies with
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#17328520438332808-522: Was derived and ported by VAST Corporation from AT&T 3B20 Unix SysVr3 code used internally within AT&;T. Earlier non-commercial multiprocessing UNIX ports existed, including a port named MUNIX created at the Naval Postgraduate School by 1975. Time-sharing and server systems can often use SMP without changes to applications, as they may have multiple processes running in parallel, and
2862-536: Was released, though it is unclear what, if any, heritage this Opteron-branded product line shares with the original Opteron technology other than intended use in the server space. Opteron combines two important capabilities in a single processor: The first capability is notable because at the time of Opteron's introduction, the only other 64-bit architecture marketed with 32-bit x86 compatibility (Intel's Itanium ) ran x86 legacy-applications only with significant speed degradation. The second capability, by itself,
2916-431: Was the model 875, with two cores running at 2.2 GHz each. AMD's fastest single-core Opteron at this time was the model 252, with one core running at 2.6 GHz. For multithreaded applications, or many single threaded applications, the model 875 would be much faster than the model 252. Second-generation Opterons are offered in three series: the 1000 Series (single socket only), the 2000 Series (dual socket-capable), and
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