Misplaced Pages

#90909

123-466: Socket G2 , also known as rPGA 988B is Intel 's CPU socket used with their line of mobile Core i7 , the successor to the Core 2 line, and also with several mobile Core i5 and Core i3 processors. It is based on Intel's Sandy Bridge and Ivy Bridge architecture. Like its predecessor, socket G1 systems, it can only run in dual-channel memory mode, but with data rates up to 1600 MHz (as opposed to

246-595: A 47% increase in the price-per-bit in 2017, the largest jump in 30 years since the 45% jump in 1988, while in recent years the price has been going down. In 2018, a "key characteristic of the DRAM market is that there are currently only three major suppliers — Micron Technology , SK Hynix and Samsung Electronics " that are "keeping a pretty tight rein on their capacity". There is also Kioxia (previously Toshiba Memory Corporation after 2017 spin-off) which doesn't manufacture DRAM. Other manufacturers make and sell DIMMs (but not

369-501: A bipolar dynamic RAM for its electronic calculator Toscal BC-1411. In 1966, Tomohisa Yoshimaru and Hiroshi Komikawa from Toshiba applied for a Japanese patent of a memory circuit composed of several transistors and a capacitor, in 1967 they applied for a patent in the US. The earliest forms of DRAM mentioned above used bipolar transistors . While it offered improved performance over magnetic-core memory , bipolar DRAM could not compete with

492-614: A capacitor are required per bit, compared to four or six transistors in SRAM. This allows DRAM to reach very high densities with a simultaneous reduction in cost per bit. Refreshing the data consumes power, causing a variety of techniques to be used to manage the overall power consumption. For this reason, DRAM usually needs to operate with a memory controller ; the memory controller needs to know DRAM parameters, especially memory timings , to initialize DRAMs, which may be different depending on different DRAM manufacturers and part numbers. DRAM had

615-466: A cost advantage that grew with every jump in memory size. The MK4096 proved to be a very robust design for customer applications. At the 16 Kbit density, the cost advantage increased; the 16 Kbit Mostek MK4116 DRAM, introduced in 1976, achieved greater than 75% worldwide DRAM market share. However, as density increased to 64 Kbit in the early 1980s, Mostek and other US manufacturers were overtaken by Japanese DRAM manufacturers, which dominated

738-437: A hard-wired dynamic memory. Paper tape was read and the characters on it "were remembered in a dynamic store." The store used a large bank of capacitors, which were either charged or not, a charged capacitor representing cross (1) and an uncharged capacitor dot (0). Since the charge gradually leaked away, a periodic pulse was applied to top up those still charged (hence the term 'dynamic')". In November 1965, Toshiba introduced

861-437: A limited group of private investors (equivalent to $ 21 million in 2022), convertible at $ 5 per share. Just 2 years later, Intel became a public company via an initial public offering (IPO), raising $ 6.8 million ($ 23.50 per share). Intel was one of the very first companies to be listed on the then-newly established National Association of Securities Dealers Automated Quotations ( NASDAQ ) stock exchange. Intel's third employee

984-412: A logic one requires the wordline be driven to a voltage greater than the sum of V CC and the access transistor's threshold voltage (V TH ). This voltage is called V CC pumped (V CCP ). The time required to discharge a capacitor thus depends on what logic value is stored in the capacitor. A capacitor containing logic one begins to discharge when the voltage at the access transistor's gate terminal

1107-563: A major retrenchment for most of the major semiconductor manufacturers, except for Qualcomm, which continued to see healthy purchases from its largest customer, Apple. As of July 2013, five companies were using Intel's fabs via the Intel Custom Foundry division: Achronix , Tabula , Netronome , Microsemi , and Panasonic  – most are field-programmable gate array (FPGA) makers, but Netronome designs network processors. Only Achronix began shipping chips made by Intel using

1230-616: A new microprocessor manufacturing facility in Chandler, Arizona , completed in 2013 at a cost of $ 5 billion. The building is now the 10 nm-certified Fab 42 and is connected to the other Fabs (12, 22, 32) on Ocotillo Campus via an enclosed bridge known as the Link. The company produces three-quarters of its products in the United States, although three-quarters of its revenue come from overseas. The Alliance for Affordable Internet (A4AI)

1353-676: A processor for tablets and smartphones – to the market in 2012, as an effort to compete with Arm. As a 32-nanometer processor, Medfield is designed to be energy-efficient, which is one of the core features in Arm's chips. At the Intel Developers Forum (IDF) 2011 in San Francisco, Intel's partnership with Google was announced. In January 2012, Google announced Android 2.3, supporting Intel's Atom microprocessor. In 2013, Intel's Kirk Skaugen said that Intel's exclusive focus on Microsoft platforms

SECTION 10

#1732855072091

1476-716: A reduction in Intel's dominance and market share in the PC market. Nevertheless, with a 68.4% market share as of 2023, Intel still leads the x86 market by a wide margin. In addition, Intel's ability to design and manufacture its own chips is considered a rarity in the semiconductor industry , as most chip designers do not have their own production facilities and instead rely on contract manufacturers (e.g. AMD and Nvidia ). In 2023, Dell accounted for about 19% of Intel's total revenues, Lenovo accounted for 11% of total revenues, and HP Inc. accounted for 10% of total revenues. As of May 2024,

1599-467: A single bitline contact) from a column, then move the DRAM cells from an adjacent column into the voids. The location where the bitline twists occupies additional area. To minimize area overhead, engineers select the simplest and most area-minimal twisting scheme that is able to reduce noise under the specified limit. As process technology improves to reduce minimum feature sizes, the signal to noise problem worsens, since coupling between adjacent metal wires

1722-407: A single chip, to accommodate more capacity without becoming too slow. When such a RAM is accessed by clocked logic, the times are generally rounded up to the nearest clock cycle. For example, when accessed by a 100 MHz state machine (i.e. a 10 ns clock), the 50 ns DRAM can perform the first read in five clock cycles, and additional reads within the same page every two clock cycles. This

1845-579: A standalone business unit. Unlike Intel Custom Foundry, IFS will offer a combination of packaging and process technology, and Intel's IP portfolio including x86 cores. Other plans for the company include a partnership with IBM and a new event for developers and engineers, called "Intel ON". Gelsinger also confirmed that Intel's 7 nm process is on track, and that the first products using their 7 nm process (also known as Intel 4) are Ponte Vecchio and Meteor Lake . In January 2022, Intel reportedly selected New Albany, Ohio , near Columbus, Ohio , as

1968-623: A stroke regained much of its leadership of the field. In 2008, Intel had another "tick" when it introduced the Penryn microarchitecture, fabricated using the 45 nm process node. Later that year, Intel released a processor with the Nehalem architecture to positive reception. On June 27, 2006, the sale of Intel's XScale assets was announced. Intel agreed to sell the XScale processor business to Marvell Technology Group for an estimated $ 600 million and

2091-462: A time determined by an external timer function that governs the operation of the rest of a system, such as the vertical blanking interval that occurs every 10–20 ms in video equipment. The row address of the row that will be refreshed next is maintained by external logic or a counter within the DRAM. A system that provides the row address (and the refresh command) does so to have greater control over when to refresh and which row to refresh. This

2214-444: A value is read, modified, and then written back as a single, indivisible operation (Jacob, p. 459). The one-transistor, zero-capacitor (1T, or 1T0C) DRAM cell has been a topic of research since the late-1990s. 1T DRAM is a different way of constructing the basic DRAM memory cell, distinct from the classic one-transistor/one-capacitor (1T/1C) DRAM cell, which is also sometimes referred to as 1T DRAM , particularly in comparison to

2337-450: Is 3-4-4-8 with a 200 MHz clock, while premium-priced high performance PC3200 DDR DRAM DIMM might be operated at 2-2-2-5 timing. Minimum random access time has improved from t RAC  = 50 ns to t RCD + t CL = 22.5 ns , and even the premium 20 ns variety is only 2.5 times faster than the asynchronous DRAM. CAS latency has improved even less, from t CAC = 13 ns to 10 ns. However,

2460-452: Is RISC-V , which is an open source CPU instruction set. The major Chinese phone and telecommunications manufacturer Huawei has released chips based on the RISC-V instruction set due to US sanctions against China . Intel has been involved in several disputes regarding the violation of antitrust laws , which are noted below. Intel reported total CO 2 e emissions (direct + indirect) for

2583-442: Is able to offer better long-term area efficiencies; since folded array architectures require increasingly complex folding schemes to match any advance in process technology. The relationship between process technology, array architecture, and area efficiency is an active area of research. The first DRAM integrated circuits did not have any redundancy. An integrated circuit with a defective DRAM cell would be discarded. Beginning with

SECTION 20

#1732855072091

2706-439: Is above V CCP . If the capacitor contains a logic zero, it begins to discharge when the gate terminal voltage is above V TH . Up until the mid-1980s, the capacitors in DRAM cells were co-planar with the access transistor (they were constructed on the surface of the substrate), thus they were referred to as planar capacitors. The drive to increase both density and, to a lesser extent, performance, required denser designs. This

2829-433: Is also used in many portable devices and video game consoles. In contrast, SRAM, which is faster and more expensive than DRAM, is typically used where speed is of greater concern than cost and size, such as the cache memories in processors . The need to refresh DRAM demands more complicated circuitry and timing than SRAM. This complexity is offset by the structural simplicity of DRAM memory cells: only one transistor and

2952-456: Is associated with the executive leadership and vision of Andrew Grove . The company was a key component of the rise of Silicon Valley as a high-tech center, as well as being an early developer of SRAM and DRAM memory chips, which represented the majority of its business until 1981. Although Intel created the world's first commercial microprocessor chip—the Intel 4004 —in 1971, it was not until

3075-517: Is considered one of the world's largest semiconductor chip manufacturers by revenue and ranked in the Fortune 500 list of the largest United States corporations by revenue for nearly a decade, from 2007 to 2016 fiscal years, until it was removed from the ranking in 2018. In 2020, it was reinstated and ranked 45th, being the 7th-largest technology company in the ranking . Intel supplies microprocessors for most manufacturers of computer systems, and

3198-413: Is done to minimize conflicts with memory accesses, since such a system has both knowledge of the memory access patterns and the refresh requirements of the DRAM. When the row address is supplied by a counter within the DRAM, the system relinquishes control over which row is refreshed and only provides the refresh command. Some modern DRAMs are capable of self-refresh; no external logic is required to instruct

3321-438: Is expected to affect Intel minimally; however, it might prompt other PC manufacturers to reevaluate their reliance on Intel and the x86 architecture. On March 23, 2021, CEO Pat Gelsinger laid out new plans for the company. These include a new strategy, called IDM 2.0, that includes investments in manufacturing facilities, use of both internal and external foundries, and a new foundry business called Intel Foundry Services (IFS),

3444-436: Is fully at its highest voltage and the other bit-line is at the lowest possible voltage. To store data, a row is opened and a given column's sense amplifier is temporarily forced to the desired high or low-voltage state, thus causing the bit-line to charge or discharge the cell storage capacitor to the desired value. Due to the sense amplifier's positive feedback configuration, it will hold a bit-line at stable voltage even after

3567-405: Is given as n F , where n is a number derived from the DRAM cell design, and F is the smallest feature size of a given process technology. This scheme permits comparison of DRAM size over different process technology generations, as DRAM cell area scales at linear or near-linear rates with respect to feature size. The typical area for modern DRAM cells varies between 6–8 F . The horizontal wire,

3690-424: Is inversely proportional to their pitch. The array folding and bitline twisting schemes that are used must increase in complexity in order to maintain sufficient noise reduction. Schemes that have desirable noise immunity characteristics for a minimal impact in area is the topic of current research (Kenner, p. 37). Advances in process technology could result in open bitline array architectures being favored if it

3813-408: Is limited by its capacitance (which increases with length), which must be kept within a range for proper sensing (as DRAMs operate by sensing the charge of the capacitor released onto the bitline). Bitline length is also limited by the amount of operating current the DRAM can draw and by how power can be dissipated, since these two characteristics are largely determined by the charging and discharging of

Socket G2 - Misplaced Pages Continue

3936-484: Is one of the developers of the x86 series of instruction sets found in most personal computers (PCs). It also manufactures chipsets , network interface controllers , flash memory , graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and other devices related to communications and computing. Intel has a strong presence in the high-performance general-purpose and gaming PC market with its Intel Core line of CPUs, whose high-end models are among

4059-466: Is planned for 2027. Including subcontractors, this would create 10,000 new jobs. In August 2022, Intel signed a $ 30   billion partnership with Brookfield Asset Management to fund its recent factory expansions. As part of the deal, Intel would have a controlling stake by funding 51% of the cost of building new chip-making facilities in Chandler, with Brookfield owning the remaining 49% stake, allowing

4182-489: Is the clearest way to compare between the performance of different DRAM memories, as it sets the slower limit regardless of the row length or page size. Bigger arrays forcibly result in larger bit line capacitance and longer propagation delays, which cause this time to increase as the sense amplifier settling time is dependent on both the capacitance as well as the propagation latency. This is countered in modern DRAM chips by instead integrating many more complete DRAM arrays within

4305-443: Is usually arranged in a rectangular array of charge storage cells consisting of one capacitor and transistor per data bit. The figure to the right shows a simple example with a four-by-four cell matrix. Some DRAM matrices are many thousands of cells in height and width. The long horizontal lines connecting each row are known as word-lines. Each column of cells is composed of two bit-lines, each connected to every other storage cell in

4428-450: The Intel 1103 , in October 1970, despite initial problems with low yield until the fifth revision of the masks . The 1103 was designed by Joel Karp and laid out by Pat Earhart. The masks were cut by Barbara Maness and Judy Garcia. MOS memory overtook magnetic-core memory as the dominant memory technology in the early 1970s. The first DRAM with multiplexed row and column address lines was

4551-468: The JEDEC standard. Some systems refresh every row in a burst of activity involving all rows every 64 ms. Other systems refresh one row at a time staggered throughout the 64 ms interval. For example, a system with 2  = 8,192 rows would require a staggered refresh rate of one row every 7.8 μs which is 64 ms divided by 8,192 rows. A few real-time systems refresh a portion of memory at

4674-490: The Mostek MK4096 4 Kbit DRAM designed by Robert Proebsting and introduced in 1973. This addressing scheme uses the same address pins to receive the low half and the high half of the address of the memory cell being referenced, switching between the two halves on alternating bus cycles. This was a radical advance, effectively halving the number of address lines required, which enabled it to fit into packages with fewer pins,

4797-507: The PowerPC architecture developed by the AIM alliance . This was seen as a win for Intel; an analyst called the move "risky" and "foolish", as Intel's current offerings at the time were considered to be behind those of AMD and IBM. In 2006, Intel unveiled its Core microarchitecture to widespread critical acclaim; the product range was perceived as an exceptional leap in processor performance that at

4920-587: The Semiconductor Chip Protection Act of 1984 , a law sought by Intel and the Semiconductor Industry Association (SIA). During the late 1980s and 1990s (after this law was passed), Intel also sued companies that tried to develop competitor chips to the 80386 CPU . The lawsuits were noted to significantly burden the competition with legal bills, even if Intel lost the suits. Antitrust allegations had been simmering since

5043-480: The U.S. Department of Defense is another large customer for Intel. In September 2024, Intel reportedly qualified for as much as $ 3.5 billion in federal grants to make semiconductors for the Defense Department. According to IDC , while Intel enjoyed the biggest market share in both the overall worldwide PC microprocessor market (73.3%) and the mobile PC microprocessor (80.4%) in the second quarter of 2011,

Socket G2 - Misplaced Pages Continue

5166-489: The Zen microarchitecture and a new chiplet -based design to critical acclaim. Since its introduction, AMD, once unable to compete with Intel in the high-end CPU market, has undergone a resurgence, and Intel's dominance and market share have considerably decreased. In addition, Apple began to transition away from the x86 architecture and Intel processors to their own Apple silicon for their Macintosh computers in 2020. The transition

5289-406: The dominant supplier of PC microprocessors, with a market share of 90%, and was known for aggressive and anti-competitive tactics in defense of its market position, particularly against AMD , as well as a struggle with Microsoft for control over the direction of the PC industry. Since the 2000s and especially since the late 2010s, Intel has faced increasing competition, which has led to

5412-519: The semiconductor memory market, widely predicted to replace magnetic-core memory . Its first product, a quick entry into the small, high-speed memory market in 1969, was the 3101 Schottky TTL bipolar 64-bit static random-access memory (SRAM), which was nearly twice as fast as earlier Schottky diode implementations by Fairchild and the Electrotechnical Laboratory in Tsukuba, Japan . In

5535-475: The triple-channel mode which is unique to the LGA-1366 platform and subsequent Xeon sockets). Socket G2 CPUs are also known as FCPGA988 socket processors, which should be pin compatible with PPGA988. Although nearly all motherboards using this socket are intended for mobile products like laptops, a few desktop boards using this do exist. Supermicro , for example, produced a number of mini ITX motherboards using

5658-457: The x86 processor market is AMD, with which Intel has had full cross-licensing agreements since 1976: each partner can use the other's patented technological innovations without charge after a certain time. However, the cross-licensing agreement is canceled in the event of an AMD bankruptcy or takeover. Some smaller competitors, such as VIA Technologies, produce low-power x86 processors for small factor computers and portable equipment. However,

5781-404: The /RAS low to valid data out time. This is the time to open a row, settle the sense amplifiers, and deliver the selected column data to the output. This is also the minimum /RAS low time, which includes the time for the amplified data to be delivered back to recharge the cells. The time to read additional bits from an open page is much less, defined by the /CAS to /CAS cycle time. The quoted number

5904-459: The 22 nm Tri-Gate process. Several other customers also exist but were not announced at the time. The foundry business was closed in 2018 due to Intel's issues with its manufacturing. Intel continued its tick-tock model of a microarchitecture change followed by a die shrink until the 6th-generation Core family based on the Skylake microarchitecture. This model was deprecated in 2016, with

6027-504: The 3T and 4T DRAM which it replaced in the 1970s. In 1T DRAM cells, the bit of data is still stored in a capacitive region controlled by a transistor, but this capacitance is no longer provided by a separate capacitor. 1T DRAM is a "capacitorless" bit cell design that stores data using the parasitic body capacitance that is inherent to silicon on insulator (SOI) transistors. Considered a nuisance in logic design, this floating body effect can be used for data storage. This gives 1T DRAM cells

6150-464: The 3T1C cell for performance reasons (Kenner, p. 6). These performance advantages included, most significantly, the ability to read the state stored by the capacitor without discharging it, avoiding the need to write back what was read out (non-destructive read). A second performance advantage relates to the 3T1C cell's separate transistors for reading and writing; the memory controller can exploit this feature to perform atomic read-modify-writes, where

6273-462: The 64 Kbit generation, DRAM arrays have included spare rows and columns to improve yields. Spare rows and columns provide tolerance of minor fabrication defects which have caused a small number of rows or columns to be inoperable. The defective rows and columns are physically disconnected from the rest of the array by a triggering a programmable fuse or by cutting the wire by a laser. The spare rows or columns are substituted in by remapping logic in

SECTION 50

#1732855072091

6396-498: The DDR3 memory does achieve 32 times higher bandwidth; due to internal pipelining and wide data paths, it can output two words every 1.25 ns (1 600  Mword/s) , while the EDO DRAM can output one word per t PC  = 20 ns (50 Mword/s). Each bit of data in a DRAM is stored as a positive or negative electrical charge in a capacitive structure. The structure providing

6519-514: The DRAM chips in them), such as Kingston Technology , and some manufacturers that sell stacked DRAM (used e.g. in the fastest supercomputers on the exascale ), separately such as Viking Technology . Others sell such integrated into other products, such as Fujitsu into its CPUs, AMD in GPUs, and Nvidia , with HBM2 in some of their GPU chips. The cryptanalytic machine code-named Aquarius used at Bletchley Park during World War II incorporated

6642-400: The DRAM to refresh or to provide a row address. Under some conditions, most of the data in DRAM can be recovered even if the DRAM has not been refreshed for several minutes. Many parameters are required to fully describe the timing of DRAM operation. Here are some examples for two timing grades of asynchronous DRAM, from a data sheet published in 1998: Thus, the generally quoted number is

6765-611: The QM77 chipset. rPGA 989 (as shown on the right) is a socket that can take Socket G1 (rPGA988A) or Socket G2 (rPGA988B) processors. Supported memory: Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California , and incorporated in Delaware . Intel designs, manufactures, and sells computer components and related products for business and consumer markets. It

6888-595: The UN Broadband Commission's worldwide target of 5% of monthly income. In April 2011, Intel began a pilot project with ZTE Corporation to produce smartphones using the Intel Atom processor for China's domestic market. In December 2011, Intel announced that it reorganized several of its business units into a new mobile and communications group that would be responsible for the company's smartphone, tablet, and wireless efforts. Intel planned to introduce Medfield –

7011-536: The US and worldwide markets during the 1980s and 1990s. Early in 1985, Gordon Moore decided to withdraw Intel from producing DRAM. By 1986, many, but not all, United States chip makers had stopped making DRAMs. Micron Technology and Texas Instruments continued to produce them commercially, and IBM produced them for internal use. In 1985, when 64K DRAM memory chips were the most common memory chips used in computers, and when more than 60 percent of those chips were produced by Japanese companies, semiconductor makers in

7134-484: The United States accused Japanese companies of export dumping for the purpose of driving makers in the United States out of the commodity memory chip business. Prices for the 64K product plummeted to as low as 35 cents apiece from $ 3.50 within 18 months, with disastrous financial consequences for some U.S. firms. On 4 December 1985 the US Commerce Department's International Trade Administration ruled in favor of

7257-682: The United States. Intel was incorporated in Mountain View, California , on July 18, 1968, by Gordon E. Moore (known for " Moore's law "), a chemist ; Robert Noyce , a physicist and co-inventor of the integrated circuit ; and Arthur Rock , an investor and venture capitalist . Moore and Noyce had left Fairchild Semiconductor , where they were part of the " traitorous eight " who founded it. There were originally 500,000 shares outstanding of which Dr. Noyce bought 245,000 shares, Dr. Moore 245,000 shares, and Mr. Rock 10,000 shares; all at $ 1 per share. Rock offered $ 2,500,000 of convertible debentures to

7380-464: The Xeon 6 processor, aiming for better performance and power efficiency compared to its predecessor. Intel's Gaudi 2 and Gaudi 3 AI accelerators were revealed to be more cost-effective than competitors' offerings. Additionally, Intel disclosed architecture details for its Lunar Lake processors for AI PCs, which were released on September 24, 2024. Dynamic random-access memory DRAM typically takes

7503-584: The advent of such mobile computing devices, in particular, smartphones , has led to a decline in PC sales . Since over 95% of the world's smartphones currently use processors cores designed by Arm , using the Arm instruction set , Arm has become a major competitor for Intel's processor market. Arm is also planning to make attempts at setting foot into the PC and server market, with Ampere and IBM each individually designing CPUs for servers and supercomputers . The only other major competitor in processor instruction sets

SECTION 60

#1732855072091

7626-402: The assumption of unspecified liabilities. The move was intended to permit Intel to focus its resources on its core x86 and server businesses, and the acquisition completed on November 9, 2006. In 2008, Intel spun off key assets of a solar startup business effort to form an independent company, SpectraWatt Inc. In 2011, SpectraWatt filed for bankruptcy. In February 2011, Intel began to build

7749-476: The bitline, which is almost always made of polysilicon, but is otherwise identical to the COB variation. The advantage the COB variant possesses is the ease of fabricating the contact between the bitline and the access transistor's source as it is physically close to the substrate surface. However, this requires the active area to be laid out at a 45-degree angle when viewed from above, which makes it difficult to ensure that

7872-415: The bitline. Sense amplifiers are required to read the state contained in the DRAM cells. When the access transistor is activated, the electrical charge in the capacitor is shared with the bitline. The bitline's capacitance is much greater than that of the capacitor (approximately ten times). Thus, the change in bitline voltage is minute. Sense amplifiers are required to resolve the voltage differential into

7995-436: The bitlines are divided into multiple segments, and the differential sense amplifiers are placed in between bitline segments. Because the sense amplifiers are placed between bitline segments, to route their outputs outside the array, an additional layer of interconnect placed above those used to construct the wordlines and bitlines is required. The DRAM cells that are on the edges of the array do not have adjacent segments. Since

8118-417: The capacitance can be increased by etching a deeper hole without any increase to surface area (Kenner, p. 44). Another advantage of the trench capacitor is that its structure is under the layers of metal interconnect, allowing them to be more easily made planar, which enables it to be integrated in a logic-optimized process technology, which have many levels of interconnect above the substrate. The fact that

8241-406: The capacitance, as well as the transistors that control access to it, is collectively referred to as a DRAM cell . They are the fundamental building block in DRAM arrays. Multiple DRAM memory cell variants exist, but the most commonly used variant in modern DRAMs is the one-transistor, one-capacitor (1T1C) cell. The transistor is used to admit current into the capacitor during writes, and to discharge

8364-410: The capacitor contact does not touch the bitline. CUB cells avoid this, but suffer from difficulties in inserting contacts in between bitlines, since the size of features this close to the surface are at or near the minimum feature size of the process technology (Kenner, pp. 33–42). The trench capacitor is constructed by etching a deep hole into the silicon substrate. The substrate volume surrounding

8487-417: The capacitor during reads. The access transistor is designed to maximize drive strength and minimize transistor-transistor leakage (Kenner, p. 34). The capacitor has two terminals, one of which is connected to its access transistor, and the other to either ground or V CC /2. In modern DRAMs, the latter case is more common, since it allows faster operation. In modern DRAMs, a voltage of +V CC /2 across

8610-405: The capacitor is required to store a logic one; and a voltage of −V CC /2 across the capacitor is required to store a logic zero. The resultant charge is Q = ± V C C 2 ⋅ C {\textstyle Q=\pm {V_{CC} \over 2}\cdot C} , where Q is the charge in coulombs and C is the capacitance in farads . Reading or writing

8733-410: The capacitor is under the logic means that it is constructed before the transistors are. This allows high-temperature processes to fabricate the capacitors, which would otherwise degrade the logic transistors and their performance. This makes trench capacitors suitable for constructing embedded DRAM (eDRAM) (Jacob, p. 357). Disadvantages of trench capacitors are difficulties in reliably constructing

8856-426: The capacitor to the write bitline just as in the 1T1C cell, but there was a separate read wordline and read transistor which connected an amplifier transistor to the read bitline. By the second generation, the drive to reduce cost by fitting the same amount of bits in a smaller area led to the almost universal adoption of the 1T1C DRAM cell, although a couple of devices with 4 and 16 Kbit capacities continued to use

8979-404: The capacitor's structures within deep holes and in connecting the capacitor to the access transistor's drain terminal (Kenner, p. 44). First-generation DRAM ICs (those with capacities of 1 Kbit), such as the archetypical Intel 1103 , used a three-transistor, one-capacitor (3T1C) DRAM cell with separate read and write circuitry. The write wordline drove a write transistor which connected

9102-482: The column (the illustration to the right does not include this important detail). They are generally known as the + and − bit lines. A sense amplifier is essentially a pair of cross-connected inverters between the bit-lines. The first inverter is connected with input from the + bit-line and output to the − bit-line. The second inverter's input is from the − bit-line with output to the + bit-line. This results in positive feedback which stabilizes after one bit-line

9225-586: The commercialized Z-RAM from Innovative Silicon, the TTRAM from Renesas and the A-RAM from the UGR / CNRS consortium. DRAM cells are laid out in a regular rectangular, grid-like pattern to facilitate their control and access via wordlines and bitlines. The physical layout of the DRAM cells in an array is typically designed so that two adjacent DRAM cells in a column share a single bitline contact to reduce their area. DRAM cell area

9348-420: The companies to split the revenue from those facilities. On January 31, 2023, as part of $ 3 billion in cost reductions, Intel announced pay cuts affecting employees above midlevel, ranging from 5% upwards. It also suspended bonuses and merit pay increases, while reducing retirement plan matching. These cost reductions followed layoffs announced in the fall of 2022. In October 2023, Intel confirmed it would be

9471-451: The company as NM Electronics on July 18, 1968, but by the end of the month had changed the name to Intel , which stood for Int egrated El ectronics. Since "Intel" was already trademarked by the hotel chain Intelco, they had to buy the rights for the name. At its founding, Intel was distinguished by its ability to make logic circuits using semiconductor devices . The founders' goal was

9594-425: The company's focus to microprocessors and to change fundamental aspects of that business model. Moore's decision to sole-source Intel's 386 chip played into the company's continuing success. By the end of the 1980s, buoyed by its fortuitous position as microprocessor supplier to IBM and IBM's competitors within the rapidly growing personal computer market , Intel embarked on a 10-year period of unprecedented growth as

9717-580: The complaint. Synchronous dynamic random-access memory (SDRAM) was developed by Samsung . The first commercial SDRAM chip was the Samsung KM48SL2000, which had a capacity of 16   Mb , and was introduced in 1992. The first commercial DDR SDRAM ( double data rate SDRAM) memory chip was Samsung's 64   Mb DDR SDRAM chip, released in 1998. Later, in 2001, Japanese DRAM makers accused Korean DRAM manufacturers of dumping. In 2002, US computer makers made claims of DRAM price fixing . DRAM

9840-412: The differential sense amplifiers require identical capacitance and bitline lengths from both segments, dummy bitline segments are provided. The advantage of the open bitline array is a smaller array area, although this advantage is slightly diminished by the dummy bitline segments. The disadvantage that caused the near disappearance of this architecture is the inherent vulnerability to noise , which affects

9963-560: The early 1980s, and manufacturing and development centers in China, India, and Costa Rica in the 1990s. By the early 1980s, its business was dominated by DRAM chips. However, increased competition from Japanese semiconductor manufacturers had, by 1983, dramatically reduced the profitability of this market. The growing success of the IBM personal computer, based on an Intel microprocessor, was among factors that convinced Gordon Moore (CEO since 1975) to shift

10086-506: The early 1990s and had been the cause of one lawsuit against Intel in 1991. In 2004 and 2005, AMD brought further claims against Intel related to unfair competition . In 2005, CEO Paul Otellini reorganized the company to refocus its core processor and chipset business on platforms (enterprise, digital home, digital health, and mobility). On June 6, 2005, Steve Jobs , then CEO of Apple , announced that Apple would be using Intel's x86 processors for its Macintosh computers, switching from

10209-553: The effectiveness of the differential sense amplifiers. Since each bitline segment does not have any spatial relationship to the other, it is likely that noise would affect only one of the two bitline segments. The folded bitline array architecture routes bitlines in pairs throughout the array. The close proximity of the paired bitlines provide superior common-mode noise rejection characteristics over open bitline arrays. The folded bitline array architecture began appearing in DRAM ICs during

10332-418: The fastest consumer CPUs, as well as its Intel Arc series of GPUs. The Open Source Technology Center at Intel hosts PowerTOP and LatencyTOP , and supports other open source projects such as Wayland , Mesa , Threading Building Blocks (TBB), and Xen . Intel was founded on July 18, 1968, by semiconductor pioneers Gordon Moore (of Moore's law ) and Robert Noyce , along with investor Arthur Rock , and

10455-653: The first commercial user of high-NA EUV lithography tool, as part of its plan to regain process leadership from TSMC . In August 2024, following a below-expectations Q2 earnings announcement, Intel announced "significant actions to reduce our costs. We plan to deliver $ 10 billion in cost savings in 2025, and this includes reducing our head count by roughly 15,000 roles, or 15% of our workforce." In December 2023, Intel unveiled Gaudi3, an artificial intelligence (AI) chip for generative AI software which will launch in 2024 and compete with rival chips from Nvidia and AMD. On 4 June 2024, Intel announced AI chips for data centers,

10578-445: The first commercially available dynamic random-access memory (DRAM), the 1103 released in 1970, solved these issues. The 1103 was the bestselling semiconductor memory chip in the world by 1972, as it replaced core memory in many applications. Intel's business grew during the 1970s as it expanded and improved its manufacturing processes and produced a wider range of products , still dominated by various memory devices. Intel created

10701-409: The first commercially available microprocessor, the Intel 4004 , in 1971. The microprocessor represented a notable advance in the technology of integrated circuitry, as it miniaturized the central processing unit of a computer, which then made it possible for small machines to perform calculations that in the past only very large machines could do. Considerable technological innovation was needed before

10824-418: The forcing voltage is removed. During a write to a particular cell, all the columns in a row are sensed simultaneously just as during reading, so although only a single column's storage-cell capacitor charge is changed, the entire row is refreshed (written back in), as illustrated in the figure to the right. Typically, manufacturers specify that each row must be refreshed every 64 ms or less, as defined by

10947-465: The form of an integrated circuit chip, which can consist of dozens to billions of DRAM memory cells. DRAM chips are widely used in digital electronics where low-cost and high-capacity computer memory is required. One of the largest applications for DRAM is the main memory (colloquially called the RAM) in modern computers and graphics cards (where the main memory is called the graphics memory ). It

11070-512: The greatest density as well as allowing easier integration with high-performance logic circuits since they are constructed with the same SOI process technologies. Refreshing of cells remains necessary, but unlike with 1T1C DRAM, reads in 1T DRAM are non-destructive; the stored charge causes a detectable shift in the threshold voltage of the transistor. Performance-wise, access times are significantly better than capacitor-based DRAMs, but slightly worse than SRAM. There are several types of 1T DRAMs:

11193-485: The hole is then heavily doped to produce a buried n plate with low resistance. A layer of oxide-nitride-oxide dielectric is grown or deposited, and finally the hole is filled by depositing doped polysilicon, which forms the top plate of the capacitor. The top of the capacitor is connected to the access transistor's drain terminal via a polysilicon strap (Kenner, pp. 42–44). A trench capacitor's depth-to-width ratio in DRAMs of

11316-425: The lengths of the bitlines and the number of attached DRAM cells attached to them are equal, two basic architectures to array design have emerged to provide for the requirements of the sense amplifiers: open and folded bitline arrays. The first generation (1 Kbit) DRAM ICs, up until the 64 Kbit generation (and some 256 Kbit generation devices) had open bitline array architectures. In these architectures,

11439-471: The levels specified by the logic signaling system. Modern DRAMs use differential sense amplifiers, and are accompanied by requirements as to how the DRAM arrays are constructed. Differential sense amplifiers work by driving their outputs to opposing extremes based on the relative voltages on pairs of bitlines. The sense amplifiers function effectively and efficient only if the capacitance and voltages of these bitline pairs are closely matched. Besides ensuring that

11562-643: The lower price of the then-dominant magnetic-core memory. Capacitors had also been used for earlier memory schemes, such as the drum of the Atanasoff–Berry Computer , the Williams tube and the Selectron tube . In 1966, Dr. Robert Dennard invented modern DRAM architecture in which there's a single MOS transistor per capacitor, at the IBM Thomas J. Watson Research Center , while he was working on MOS memory and

11685-526: The microprocessor could actually become the basis of what was first known as a "mini computer" and then known as a "personal computer". Intel also created one of the first microcomputers in 1973. Intel opened its first international manufacturing facility in 1972, in Malaysia , which would host multiple Intel operations, before opening assembly facilities and semiconductor plants in Singapore and Jerusalem in

11808-402: The mid-1980s, beginning with the 256 Kbit generation. This architecture is favored in modern DRAM ICs for its superior noise immunity. This architecture is referred to as folded because it takes its basis from the open array architecture from the perspective of the circuit schematic. The folded array architecture appears to remove DRAM cells in alternate pairs (because two DRAM cells share

11931-407: The mid-2000s can exceed 50:1 (Jacob, p. 357). Trench capacitors have numerous advantages. Since the capacitor is buried in the bulk of the substrate instead of lying on its surface, the area it occupies can be minimized to what is required to connect it to the access transistor's drain terminal without decreasing the capacitor's size, and thus capacitance (Jacob, pp. 356–357). Alternatively,

12054-605: The node. The first microprocessor under that node, Cannon Lake (marketed as 8th-generation Core), was released in small quantities in 2018. The company first delayed the mass production of their 10 nm products to 2017. They later delayed mass production to 2018, and then to 2019. Despite rumors of the process being cancelled, Intel finally introduced mass-produced 10 nm 10th-generation Intel Core mobile processors (codenamed " Ice Lake ") in September 2019. Intel later acknowledged that their strategy to shrink to 10 nm

12177-491: The numbers decreased by 1.5% and 1.9% compared to the first quarter of 2011. Intel's market share decreased significantly in the enthusiast market as of 2019, and they have faced delays for their 10 nm products. According to former Intel CEO Bob Swan, the delay was caused by the company's overly aggressive strategy for moving to its next node. In the 1980s, Intel was among the world's top ten sellers of semiconductors (10th in 1987 ). Along with Microsoft Windows , it

12300-670: The primary and most profitable hardware supplier to the PC industry, part of the winning 'Wintel' combination. Moore handed over his position as CEO to Andy Grove in 1987. By launching its Intel Inside marketing campaign in 1991, Intel was able to associate brand loyalty with consumer selection, so that by the end of the 1990s, its line of Pentium processors had become a household name. After 2000, growth in demand for high-end microprocessors slowed. Competitors, most notably AMD (Intel's largest competitor in its primary x86 architecture market), garnered significant market share, initially in low-end and mid-range processors but ultimately across

12423-514: The product range, and Intel's dominant position in its core market was greatly reduced, mostly due to controversial NetBurst microarchitecture. In the early 2000s then-CEO, Craig Barrett attempted to diversify the company's business beyond semiconductors, but few of these activities were ultimately successful. Bob had also for a number of years been embroiled in litigation. U.S. law did not initially recognize intellectual property rights related to microprocessor topology (circuit layouts), until

12546-531: The release of the 7th-generation Core family (codenamed Kaby Lake ), ushering in the process–architecture–optimization model . As Intel struggled to shrink their process node from 14 nm to 10 nm , processor development slowed down and the company continued to use the Skylake microarchitecture until 2020, albeit with optimizations. While Intel originally planned to introduce 10 nm products in 2016, it later became apparent that there were manufacturing issues with

12669-422: The row and column decoders (Jacob, pp. 358–361). Electrical or magnetic interference inside a computer system can cause a single bit of DRAM to spontaneously flip to the opposite state. The majority of one-off (" soft ") errors in DRAM chips occur as a result of background radiation , chiefly neutrons from cosmic ray secondaries, which may change the contents of one or more memory cells or interfere with

12792-405: The same year, Intel also produced the 3301 Schottky bipolar 1024-bit read-only memory (ROM) and the first commercial metal–oxide–semiconductor field-effect transistor (MOSFET) silicon gate SRAM chip, the 256-bit 1101. While the 1101 was a significant advance, its complex static cell structure made it too slow and costly for mainframe memories. The three- transistor cell implemented in

12915-492: The single-transistor MOS DRAM memory cell. He filed a patent in 1967, and was granted U.S. patent number 3,387,286 in 1968. MOS memory offered higher performance, was cheaper, and consumed less power, than magnetic-core memory. The patent describes the invention: "Each cell is formed, in one embodiment, using a single field-effect transistor and a single capacitor." MOS DRAM chips were commercialized in 1969 by Advanced Memory Systems, Inc of Sunnyvale, CA . This 1024 bit chip

13038-508: The site for a major new manufacturing facility. The facility will cost at least $ 20 billion. The company expects the facility to begin producing chips by 2025. The same year Intel also choose Magdeburg , Germany , as a site for two new chip mega factories for €17 billion (topping Tesla 's investment in Brandenburg ). The start of the construction was initially planned for 2023, but this has been postponed to late 2024, while production start

13161-498: The smartphone market. Finding itself with excess fab capacity after the failure of the Ultrabook to gain market traction and with PC sales declining, in 2013 Intel reached a foundry agreement to produce chips for Altera using a 14 nm process. General Manager of Intel's custom foundry division Sunit Rikhi indicated that Intel would pursue further such deals in the future. This was after poor sales of Windows 8 hardware caused

13284-399: The stacked capacitor, based on its location relative to the bitline—capacitor-under-bitline (CUB) and capacitor-over-bitline (COB). In the former, the capacitor is underneath the bitline, which is usually made of metal, and the bitline has a polysilicon contact that extends downwards to connect it to the access transistor's source terminal. In the latter, the capacitor is constructed above

13407-462: The substrate surface are referred to as trench capacitors. In the 2000s, manufacturers were sharply divided by the type of capacitor used in their DRAMs and the relative cost and long-term scalability of both designs have been the subject of extensive debate. The majority of DRAMs, from major manufactures such as Hynix , Micron Technology , Samsung Electronics use the stacked capacitor structure, whereas smaller manufacturers such Nanya Technology use

13530-449: The success of the PC in the early 1990s that this became its primary business. During the 1990s, the partnership between Microsoft Windows and Intel, known as " Wintel ", became instrumental in shaping the PC landscape and solidified Intel's position on the market. As a result, Intel invested heavily in new microprocessor designs in the mid to late 1990s, fostering the rapid growth of the computer industry . During this period, it became

13653-453: The trench capacitor structure (Jacob, pp. 355–357). The capacitor in the stacked capacitor scheme is constructed above the surface of the substrate. The capacitor is constructed from an oxide-nitride-oxide (ONO) dielectric sandwiched in between two layers of polysilicon plates (the top plate is shared by all DRAM cells in an IC), and its shape can be a rectangle, a cylinder, or some other more complex shape. There are two basic variations of

13776-400: The twelve months ending December 31, 2020, at 2,882 Kt (+94/+3.4% y-o-y). Intel plans to reduce carbon emissions 10% by 2030 from a 2020 base year. Intel has self-reported that they have Wafer fabrication plants in the United States, Ireland , and Israel. They have also self-reported that they have assembly and testing sites mostly in China, Costa Rica, Malaysia, and Vietnam, and one site in

13899-479: The wordline, is connected to the gate terminal of every access transistor in its row. The vertical bitline is connected to the source terminal of the transistors in its column. The lengths of the wordlines and bitlines are limited. The wordline length is limited by the desired performance of the array, since propagation time of the signal that must transverse the wordline is determined by the RC time constant . The bitline length

14022-408: Was Andy Grove , a chemical engineer , who later ran the company through much of the 1980s and the high-growth 1990s. In deciding on a name, Moore and Noyce quickly rejected "Moore Noyce", near homophone for "more noise" – an ill-suited name for an electronics company, since noise in electronics is usually undesirable and typically associated with bad interference . Instead, they founded

14145-547: Was a thing of the past and that they would now support all "tier-one operating systems" such as Linux, Android, iOS, and Chrome. In 2014, Intel cut thousands of employees in response to "evolving market trends", and offered to subsidize manufacturers for the extra costs involved in using Intel chips in their tablets. In April 2016, Intel cancelled the SoFIA platform and the Broxton Atom SoC for smartphones, effectively leaving

14268-431: Was generally described as "5-2-2-2" timing, as bursts of four reads within a page were common. When describing synchronous memory, timing is described by clock cycle counts separated by hyphens. These numbers represent t CL - t RCD - t RP - t RAS in multiples of the DRAM clock cycle time. Note that this is half of the data transfer rate when double data rate signaling is used. JEDEC standard PC3200 timing

14391-455: Was launched in October 2013 and Intel is part of the coalition of public and private organizations that also includes Facebook , Google , and Microsoft . Led by Sir Tim Berners-Lee , the A4AI seeks to make Internet access more affordable so that access is broadened in the developing world, where only 31% of people are online. Google will help to decrease Internet access prices so that they fall below

14514-955: Was part of the " Wintel " personal computer domination in the 1990s and early 2000s. In 1992, Intel became the biggest semiconductor chip maker by revenue and held the position until 2018 when Samsung Electronics surpassed it, but Intel returned to its former position the year after. Other major semiconductor companies include TSMC , GlobalFoundries , Texas Instruments , ASML , STMicroelectronics , United Microelectronics Corporation (UMC), Micron , SK Hynix , Kioxia , and SMIC . Intel's competitors in PC chipsets included AMD , VIA Technologies , Silicon Integrated Systems , and Nvidia . Intel's competitors in networking include NXP Semiconductors , Infineon , Broadcom Limited , Marvell Technology Group and Applied Micro Circuits Corporation , and competitors in flash memory included Spansion , Samsung Electronics, Qimonda , Kioxia, STMicroelectronics, Micron , and SK Hynix . The only major competitor in

14637-401: Was reported that all Intel processors made since 1995 (besides Intel Itanium and pre-2013 Intel Atom ) had been subject to two security flaws dubbed Meltdown and Spectre. Due to Intel's issues with its 10 nm process node and the company's slow processor development, the company now found itself in a market with intense competition. The company's main competitor, AMD, introduced

14760-414: Was sold to Honeywell , Raytheon , Wang Laboratories , and others. The same year, Honeywell asked Intel to make a DRAM using a three-transistor cell that they had developed. This became the Intel 1102 in early 1970. However, the 1102 had many problems, prompting Intel to begin work on their own improved design, in secrecy to avoid conflict with Honeywell. This became the first commercially available DRAM,

14883-477: Was strongly motivated by economics, a major consideration for DRAM devices, especially commodity DRAMs. The minimization of DRAM cell area can produce a denser device and lower the cost per bit of storage. Starting in the mid-1980s, the capacitor was moved above or below the silicon substrate in order to meet these objectives. DRAM cells featuring capacitors above the substrate are referred to as stacked or folded plate capacitors. Those with capacitors buried beneath

15006-428: Was too aggressive. While other foundries used up to four steps in 10 nm or 7 nm processes, the company's 10 nm process required up to five or six multi-pattern steps. In addition, Intel's 10 nm process is denser than its counterpart processes from other foundries. Since Intel's microarchitecture and process node development were coupled, processor development stagnated. In early January 2018, it

15129-456: Was trying to create an alternative to SRAM which required six MOS transistors for each bit of data. While examining the characteristics of MOS technology, he found it was capable of building capacitors, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of

#90909