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45-616: SSSE3 was first introduced with Intel processors based on the Core microarchitecture on June 26, 2006 with the "Woodcrest" Xeons. SSSE3 has been referred to by the codenames Tejas New Instructions (TNI) or Merom New Instructions (MNI) for the first processor designs intended to support it. SSSE3 has enhanced for HD audio/video decoding/encoding, for example AAC . SSSE3 contains 16 new discrete instructions. Each instruction can act on 64-bit MMX or 128-bit XMM registers. Therefore, Intel's materials refer to 32 new instructions. They include: In

90-554: A conditional jump would become a single micro-op. However, this technology does not work in 64-bit mode. Core can speculatively execute loads ahead of preceding stores with unknown addresses. Other new technologies include 1 cycle throughput (2 cycles previously) of all 128-bit SSE instructions and a new power saving design. All components will run at minimum speed, raising speed dynamically as needed (similar to AMD's Cool'n'Quiet power-saving technology, and Intel's own SpeedStep technology from earlier mobile processors). This allows

135-460: A different socket in May 2007. The desktop-oriented Conroe began with models having an FSB of 800 MT/s or 1066 MT/s with a 1333 MT/s line officially launched on July 22, 2007. The power use of these processors is very low: average energy use is to be in the 1–2 watt range in ultra low voltage variants, with thermal design powers (TDPs) of 65 watts for Conroe and most Woodcrests, 80 watts for

180-536: A new power delivery feature set specified in Voltage Regulator-Down (VRD) 11.0 . This requirement is a result of Conroe's significantly lower power consumption, compared to the Pentium 4/D CPUs it replaced. A motherboard that has both a supporting chipset and VRD 11 supports Conroe processors, but even then some boards will need an updated BIOS to recognize Conroe's FID (Frequency ID) and VID (Voltage ID). Unlike

225-525: A reduced cache size use a separate naming scheme, which means that the releases are no longer in alphabetic order. Added steppings have been used in internal and engineering samples, but are unlisted in the tables. Many of the high-end Core 2 and Xeon processors use Multi-chip modules of two chips in order to get larger cache sizes or more than two cores. Early ES/QS steppings are: B0 (CPUID 6F4h), B1 (6F5h) and E0 (6F9h). Steppings B2/B3, E1, and G0 of model 15 (cpuid 06fx) processors are evolutionary steps of

270-557: Is a multi-core processor microarchitecture launched by Intel in mid-2006. It is a major evolution over the Yonah , the previous iteration of the P6 microarchitecture series which started in 1995 with Pentium Pro . It also replaced the NetBurst microarchitecture, which suffered from high power consumption and heat intensity due to an inefficient pipeline designed for high clock rate . In early 2004

315-483: Is commonly called Penryn-3M and Wolfdale-3M and Yorkfield-6M, respectively. The single-core version of Penryn, listed as Penryn-L here, is not a separate model like Merom-L but a version of the Penryn-3M model with only one active core. The Xeon "Dunnington" processor (CPUID Family 6, model 29) is closely related to Wolfdale but comes with six cores and an on-chip L3 cache and is designed for servers with Socket 604, so it

360-407: Is marketed only as Xeon, not as Core 2. The Core microarchitecture uses several stepping levels (steppings), which unlike prior microarchitectures, represent incremental improvements, and different sets of features like cache size and low power modes. Most of these steppings are used across brands, typically by disabling some features and limiting clock frequencies on low-end chips. Steppings with

405-556: Is required in their kernels. Windows 8 and later also refuses to boot on these processors for the same reason, as they specifically require PAE support to run properly. The Yonah CPU was launched in January 2006 under the Core brand. Single and dual-core mobile version were sold under the Core Solo, Core Duo, and Pentium Dual-Core brands, and a server version was released as Xeon LV . These processors provided partial solutions to some of

450-423: Is that installing interleaved RAM will offer double the bandwidth. However, at most the increase in bandwidth by installing interleaved RAM is roughly 5–10%. The AGTL+ PSB used by all NetBurst processors and current and medium-term (pre- QuickPath ) Core 2 processors provide a 64-bit data path. Current chipsets provide for a couple of either DDR2 or DDR3 channels. On jobs requiring large amounts of memory access,

495-499: Is there a significant performance increase. While DDR2 memory models with tighter timing specifications do improve performance, the difference in real world games and applications is often negligible. Optimally, the memory bandwidth afforded should match the bandwidth of the FSB, that is to say that a CPU with a 533 MT/s rated bus speed should be paired with RAM matching the same rated speed, for example DDR2 533, or PC2-4200. A common myth

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540-536: The CPU power dissipation tables. Like the last NetBurst CPUs, Core based processors feature multiple cores and hardware virtualization support (marketed as Intel VT-x ), and Intel 64 and SSSE3 . However, Core-based processors do not have the hyper-threading technology as in Pentium 4 processors. This is because the Core microarchitecture is based on the P6 microarchitecture used by Pentium Pro, II, III, and M. The L1 cache of

585-562: The Nehalem microarchitecture . While the Core microarchitecture is a major architectural revision, it is based in part on the Pentium M processor family designed by Intel Israel. The pipeline of Core/ Penryn is 14 stages long – less than half of Prescott 's. Penryn's successor Nehalem has a two cycles higher branch misprediction penalty than Core/Penryn. Core can ideally sustain up to 4 instructions per cycle (IPC) execution rate, compared to

630-459: The Pentium M 's shortcomings by adding: This resulted in the interim microarchitecture for low-voltage only CPUs, part way between P6 and the following Core microarchitecture. On July 27, 2006, the Core microarchitecture , a derivative of P6, was launched in form of the Core 2 processor. Subsequently, more processors were released with the Core microarchitecture under Core 2, Xeon , Pentium and Celeron brand names. The Core microarchitecture

675-703: The 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn (Socket P), Wolfdale (LGA 775) and Yorkfield (MCM, LGA 775), some of which are also sold as Celeron, Pentium and Xeon processors. In the Xeon brand, the Wolfdale-DP and Harpertown code names are used for LGA 771 based MCMs with two or four active Wolfdale cores. Architecturally, 45 nm Core 2 processors feature SSE4.1 and new divide/shuffle engine. The chips come in two sizes, with 6 MB and 3 MB L2 cache. The smaller version

720-417: The 3 IPC capability of P6 , Pentium M and NetBurst microarchitectures. The new architecture is a dual core design with a shared L2 cache engineered for maximum performance per watt and improved scalability. One new technology included in the design is Macro-Ops Fusion , which combines two x86 instructions into a single micro-operation . For example, a common code sequence like a compare followed by

765-619: The 3.0 GHz Woodcrest, and 40 or 35 watts for the low-voltage Woodcrest. In comparison, a 2.2 GHz AMD Opteron 875HE processor consumes 55 watts, while the energy efficient Socket AM2 line fits in the 35 watt thermal envelope (specified a different way so not directly comparable). Merom, the mobile variant, is listed at 35 watts TDP for standard versions and 5 watts TDP for ultra low voltage (ULV) versions. Previously, Intel announced that it would now focus on power efficiency, rather than raw performance. However, at Intel Developer Forum (IDF) in spring 2006, Intel advertised both. Some of

810-540: The Core microarchitecture at 64 KB L1 cache/core (32 KB L1 Data + 32 KB L1 Instruction) is as large as in Pentium M, up from 32 KB on Pentium II / III (16 KB L1 Data + 16 KB L1 Instruction). The consumer version also lacks an L3 cache as in the Gallatin core of the Pentium 4 Extreme Edition, though it is exclusively present in high-end versions of Core-based Xeons. Both an L3 cache and hyper-threading were reintroduced again to consumer line in

855-507: The Mobile Intel 965 Express ( Santa Rosa ) platform with Socket P , while the earlier B2 and L2 steppings only appear for the Socket M based Mobile Intel 945 Express ( Napa refresh ) platform. The model 22 stepping A1 (cpuid 10661h) marks a significant design change, with just a single core and 1 MB L2 cache further reducing the power consumption and manufacturing cost for the low-end. Like

900-551: The Mobile Pentium 4 clocked over 1 GHz higher (the fastest-clocked Mobile Pentium 4 compared to the fastest-clocked Pentium M) and equipped with much more memory and bus bandwidth. The first Pentium M family processors ("Banias") internally support PAE but do not show the PAE support flag in their CPUID information; this causes some operating systems (primarily Linux distributions) to refuse to boot on such processors since PAE support

945-611: The Penryn technology, and the QX9775 is only compatible with the Intel D5400XS motherboard. The Wolfdale-3M model E7200 also has limited compatibility (at least the Xpress 200 chipset is incompatible ). Although a motherboard may have the required chipset to support Conroe, some motherboards based on the above-mentioned chipsets do not support Conroe. This is because all Conroe-based processors require

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990-546: The Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is also derived from P6. P6 was used within Intel's mainstream offerings from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC). The P6 core was the sixth generation Intel microprocessor in

1035-510: The Xeon brand. The Conroe-L and Merom-L processors are based around the same core as Conroe and Merom, but only contain a single core and 1 MB of L2 cache, significantly reducing production cost and power consumption of the processor at the expense of performance compared to the dual-core version. It is used only in ultra-low voltage Core 2 Solo U2xxx and in Celeron processors and is identified as CPUID family 6 model 22. In Intel's Tick-Tock cycle,

1080-477: The chip to produce less heat, and minimize power use. For most Woodcrest CPUs, the front-side bus (FSB) runs at 1333 MT/s ; however, this is scaled down to 1066 MT/s for lower end 1.60 and 1.86 GHz variants. The Merom mobile variant was initially targeted to run at an FSB of 667 MT/s while the second wave of Meroms, supporting 800 MT/s FSB, were released as part of the Santa Rosa platform with

1125-415: The choice of a short and efficient pipeline, delivering superior performance despite not reaching the high clocks of NetBurst. The first processors that used this architecture were code-named ' Merom ', ' Conroe ', and ' Woodcrest '; Merom is for mobile computing, Conroe is for desktop systems, and Woodcrest is for servers and workstations. While architecturally identical, the three processor lines differ in

1170-535: The coming months" with information on recommended methods of managing the translation lookaside buffer (TLB) for Core 2 to avoid issues, and admits that, "in rare instances, improper TLB invalidation may result in unpredictable system behavior, such as hangs or incorrect data." Among the issues stated: Intel errata Ax39, Ax43, Ax65, Ax79, Ax90, Ax99 are said to be particularly serious. 39, 43, 79, which can cause unpredictable behavior or system hang, have been fixed in recent steppings . Among those who have stated

1215-513: The cooling system complexity, but also the all-important battery life. Intel went back to the drawing board for a design that would be optimally suited for this market segment. The result was a modernized P6 design called the Pentium M . Design Overview The Pentium M was the most power efficient x86 processor for notebooks for several years, consuming a maximum of 27 watts at maximum load and 4-5 watts while idle. The processing efficiency gains brought about by its modernization allowed it to rival

1260-432: The earlier steppings, A1 is not used with the Mobile Intel 965 Express platform. Steppings G0, M0 and A1 mostly replaced all older steppings in 2008. In 2009, a new stepping G2 was introduced to replace the original stepping B2. In the model 23 (cpuid 01067xh), Intel started marketing stepping with full (6 MB) and reduced (3 MB) L2 cache at the same time, and giving them identical cpuid values. All steppings have

1305-503: The errata to be particularly serious are OpenBSD 's Theo de Raadt and DragonFly BSD 's Matthew Dillon . Taking a contrasting view was Linus Torvalds , calling the TLB issue "totally insignificant", adding, "The biggest problem is that Intel should just have documented the TLB behavior better." Microsoft has issued update KB936357 to address the errata by microcode update, with no performance penalty. BIOS updates are also available to fix

1350-542: The issue. P6 (microarchitecture) The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture , implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is frequently referred to as i686 . It was planned to be succeeded by the NetBurst microarchitecture used by the Pentium 4 in 2000, but was revived for the Pentium M line of microprocessors. The successor to

1395-459: The lower available memory bandwidth. The Core 2 memory management unit (MMU) in X6800, E6000 and E4000 processors does not operate to prior specifications implemented in prior generations of x86 hardware. This may cause problems, many of them serious security and stability issues, with extant operating system software. Intel's documentation states that their programming manuals will be updated "in

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1440-455: The mobile and desktop processors come in two variants that differ in the size of the L2 cache, but the specific amount of L2 cache in a product can also be reduced by disabling parts at production time. Tigerton dual-cores and all quad-core processors except - are multi-chip modules combining two dies. For the 65 nm processors, the same product code can be shared by processors with different dies, but

1485-565: The new SSE4.1 instructions. Stepping C1/M1 was a bug fix version of C0/M0 specifically for quad core processors and only used in those. Stepping E0/R0 adds two new instructions (XSAVE/XRSTOR) and replaces all earlier steppings. In mobile processors, stepping C0/M0 is only used in the Intel Mobile 965 Express ( Santa Rosa refresh ) platform, whereas stepping E0/R0 supports the later Intel Mobile 4 Express ( Montevina ) platform. Model 30 stepping A1 (cpuid 106d1h) adds an L3 cache and six instead of

1530-491: The new version of NetBurst (Prescott) needed very high power to reach the clocks it needed for competitive performance, making it unsuitable for the shift to dual/multi-core CPUs. On May 7, 2004 Intel confirmed the cancellation of the next NetBurst, Tejas and Jayhawk . Intel had been developing Merom, the 64-bit evolution of the Pentium M , since 2001, and decided to expand it to all market segments, replacing NetBurst in desktop computers and servers. It inherited from Pentium M

1575-420: The preceding NetBurst microarchitecture of the Pentium 4 and D -branded CPUs. The Core microarchitecture provides more efficient decoding stages, execution units, caches , and buses , reducing the power consumption of Core 2-branded CPUs while increasing their processing capacity. Intel's CPUs have varied widely in power consumption according to clock rate, architecture, and semiconductor process, shown in

1620-456: The prior Pentium 4 and Pentium D design, the Core 2 technology sees a greater benefit from memory running synchronously with the front-side bus (FSB). This means that for the Conroe CPUs with FSB of 1066 MT/s, the ideal memory performance for DDR2 is PC2-8500 . In a few configurations, using PC2-5300 instead of PC2-4200 can actually decrease performance. Only when going to PC2-6400

1665-475: The promised numbers were: The processors of the Core microarchitecture can be categorized by number of cores, cache size, and socket; each combination of these has a unique code name and product code that is used across several brands. For instance, code name "Allendale" with product code 80557 has two cores, 2 MB L2 cache and uses the desktop socket 775, but has been marketed as Celeron, Pentium, Core 2, and Xeon, each with different sets of features enabled. Most of

1710-527: The quad-core Core 2 processors can benefit significantly from using PC2-8500 memory, which runs at the same speed as the CPU's FSB; this is not an officially supported configuration, but several motherboards support it. The Core 2 processor does not require the use of DDR2. While the Intel 975X and P965 chipsets require this memory, some motherboards and chipsets support both Core 2 processors and DDR memory. When using DDR memory, performance may be reduced because of

1755-434: The socket used, bus speed, and power consumption. The first Core-based desktop and mobile processors were branded Core 2 , later expanding to the lower-end Pentium Dual-Core , Pentium and Celeron brands; while server and workstation Core-based processors were branded Xeon . The Core microarchitecture returned to lower clock rates and improved the use of both available clock cycles and power when compared with

1800-906: The specific information about which one is used can be derived from the stepping. The original Core 2 processors are based on the same dies that can be identified as CPUID Family 6 Model 15. Depending on their configuration and packaging, their code names are Conroe ( LGA 775 , 4 MB L2 cache), Allendale (LGA 775, 2 MB L2 cache), Merom ( Socket M , 4 MB L2 cache) and Kentsfield ( multi-chip module , LGA 775, 2x4MB L2 cache). Merom and Allendale processors with limited features are in Pentium Dual Core and Celeron processors, while Conroe, Allendale and Kentsfield also are sold as Xeon processors. Additional code names for processors based on this model are Woodcrest (LGA 771, 4 MB L2 cache), Clovertown (MCM, LGA 771, 2×4MB L2 cache) and Tigerton (MCM, Socket 604 , 2×4MB L2 cache), all of which are marketed only under

1845-641: The standard Merom/Conroe die with 4 MB L2 cache, with the short-lived E1 stepping only being used in mobile processors. Stepping L2 and M0 are the Allendale chips with just 2 MB L2 cache, reducing production cost and power consumption for low-end processors. The G0 and M0 steppings improve idle power consumption in C1E state and add the C2E state in desktop processors. In mobile processors, all of which support C1 through C4 idle states, steppings E1, G0, and M0 add support for

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1890-541: The table below, satsw (X) (read as 'saturate to signed word') takes a signed integer X, and converts it to −32768 if it is less than −32768, to +32767 if it is greater than 32767, and leaves it unchanged otherwise. As normal for the Intel architecture, bytes are 8 bits, words 16 bits, and dwords 32 bits; 'register' refers to an MMX or XMM vector register. Intel Core (microarchitecture) The Intel Core microarchitecture (provisionally referred to as Next Generation Micro-architecture , and developed as Merom )

1935-619: The usual two cores, which leads to an unusually large die size of 503 mm . As of February 2008, it has only found its way into the very high-end Xeon 7400 series ( Dunnington ). Conroe, Conroe XE and Allendale all use Socket LGA 775 ; however, not every motherboard is compatible with these processors. Supporting chipsets are: The Yorkfield XE model QX9770 (45 nm with 1600 MT/s FSB) has limited chipset compatibility - with only X38, P35 (with overclocking ) and some high-performance X48 and P45 motherboards being compatible. BIOS updates were gradually being released to provide support for

1980-484: The x86 line. The first implementation of the P6 core was the Pentium Pro CPU in 1995, the immediate successor to the original Pentium design (P5). P6 processors dynamically translate IA-32 instructions into sequences of buffered RISC-like micro-operations , then analyze and reorder the micro-operations to detect parallelizable operations that may be issued to more than one execution unit at once. The Pentium Pro

2025-689: Was the first x86 microprocessor designed by Intel to use this technique, though the NexGen Nx586 , introduced in 1994, did so earlier. Other features first implemented in the x86 space in the P6 core include: Upon release of the Pentium 4-M and Mobile Pentium 4, it was quickly realized that the new mobile NetBurst processors were not ideal for mobile computing. NetBurst-based processors were simply not as efficient per clock or per watt compared to their P6 predecessors. Mobile Pentium 4 processors ran much hotter than Pentium III-M processors without significant performance advantages. Its inefficiency affected not only

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