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34-520: PowerQUICC processors are used in networking, automotive, industrial, storage, printing and consumer applications. Freescale are using PowerQUICC processors as a part of their mobileGT platform. Freescale also manufactures QUICC microcontrollers based on the older 68k technology. There are four distinct lines of processors, mainly based on processing power. The MPC8xx family was Motorola's first PowerPC based embedded processors, suited for network processors and system-on-a-chip devices. The core

68-476: A virtual platform for the P4080 that can be used prior to silicon availability to develop, test, and debug software for the chip. Currently, the simulator is only for the P4080, not the other chips announced in 2008. Because of its complete set of network engines, this processor can be used for telecommunication systems (LTE eNodeB, EPC, WCDMA, BTS), so Freescale and 6WIND ported 6WIND's packet processing software to

102-550: A hardware hypervisor and can be run in symmetric or asymmetric mode meaning that the cores can run and boot operating systems together or separately, resetting and partitioning cores and datapaths independently without disturbing other operating systems and applications. The P4 series is a high performance networking platform, designed for backbone networking and enterprise level switching and routing . The P4 family offers an extreme multi-core platform, with support for up to eight e500mc cores at frequencies up to 1.5 GHz on

136-457: A hardware hypervisor and can be run in symmetric or asymmetric mode meaning that the cores can run and boot operating systems together or separately, resetting and partitioning cores and datapaths independently without disturbing other operating systems and applications. To help software developers and system designers get started with the QorIQ P4080, Freescale worked with Virtutech to create

170-504: A higher performance level than LS1, and it does not indicate a second generation. The middle two digits of the product name are core count; the last digit distinguishes models, with, in most but not all cases, a higher digit meaning greater performance. “A” at the end indicates the Arm processor. LX designates the 16 nm FinFET generation. The LS1 family is built on the Layerscape architecture

204-408: A network processor system architecture said to give the flexibility and scalability required by network infrastructure OEMs to handle the market trends of connected devices, massive datasets, tight security, real-time service and increasingly unpredictable network traffic patterns. Engine The QorIQ P Series processors are based on e500 or e5500 cores. The P10xx series, P2010 and P2020 are based on

238-466: A newer QUICC Engine network offload engine instead of the CPM used in the original PowerQUICC I and PowerQUICC II series. The memory controller provides support for DDR and DDR2 SDRAMs. MPC83xx – All PowerQUICC II Pro processors share this common naming scheme. A trailing "E" signifies that the processors have a built in encryption module. All devices with an 834x name lacks the quicc engine, while devices with

272-541: A number like 836x has one. The PowerQUICC III processors are based on a 32-bit Power ISA v.2.03 core called e500 , introduced in 2003. It has a dual issue, seven-stage pipeline with double precision FPUs, 32/32 KiB data and instruction L1 caches, multiple Gigabit Ethernet, PCI and PCIe, RapidIO , DDR/DDR2 memory controllers, and security accelerators. Speeds ranges from 533 MHz up to 1.5 GHz. These processors target enterprise level networking and telecom applications, high end storage, printing and imaging. Some of

306-557: A queue manager scheduling on-chip events and a SerDes based on-chip high speed network configurable as multiple Gigabit Ethernet, 10 Gigabit Ethernet , RapidIO or PCIe interfaces. The P3 family processors share the same physical package with, and are also software backwards compatible with, P4 and P5. The P3 processors have 1.3 GHz 64-bit DDR3 memory controllers, 18 SerDes lanes for networking, hardware accelerators for packet handling and scheduling, regular expressions, RAID, security, cryptography and RapidIO. The cores are supported by

340-502: Is a brand of ARM -based and Power ISA –based communications microprocessors from NXP Semiconductors (formerly Freescale ). It is the evolutionary step from the PowerQUICC platform, and initial products were built around one or more e500mc cores and came in five different product platforms, P1, P2, P3, P4, and P5, segmented by performance and functionality. The platform keeps software compatibility with older PowerPC products such as

374-408: Is a programmable data-plane engine networking architecture . Both LS1 and LS2 families of processors offer the advanced, high-performance datapath and network peripheral interfaces. These features are frequently required for networking, telecom/datacom, wireless infrastructure , military and aerospace applications. Freescale Semiconductor Inc. (acquired by NXP Semiconductors in late 2015) announced

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408-476: Is an original implementation of the PowerPC specification. It is a single issue, four stage pipelined core with MMU and branch prediction unit with speeds up to 133 MHz. The MPC821 was introduced in 1995 together with MPC860 with a complete QUICC engine. A slimmed down version, MPC850 with reduced caches and IO ports came in 1997. The QUICC communication processor module (CPM) offloads networking tasks from

442-605: Is based on a 28 nm process and is pushing a very aggressive power envelope target, capping at 30 W . These are using the e6500 core with AltiVec and are expected to be shipping in 2013. QorIQ LS-1 and LS-2 families are ARM based processors using the Cortex A7 , Cortex A9 , A15 , A53 and A72 cores upon the ISA agnostic Layerscape architecture. They are available since 2013 and target low and mid range networking and wireless infrastructure applications. The Layerscape (LS) architecture

476-511: Is designed to replace the PowerQUICC II Pro and PowerQUICC III platforms. The chips include among other integrated functionality, Gigabit Ethernet controllers, two USB 2.0 controllers, a security engine, a 32-bit DDR2 and DDR3 memory controller with ECC support, dual four-channel DMA controllers, a SD / MMC host controller and high speed interfaces which can be configured as SerDes lanes, PCIe and SGMII interfaces. The chip

510-574: Is designed to replace the PowerQUICC II Pro and PowerQUICC III platforms. The chips include, among other integrated functionality, a 512 kB L2 cache, a security engine, three Gigabit Ethernet controllers, a USB 2.0 controller, a 64-bit DDR2 and DDR3 memory controller with ECC support, dual four-channel DMA controllers, a SD / MMC host controller and high speed SerDes lanes which can be configured as three PCIe interfaces, two RapidIO interfaces and two SGMII interfaces. The chips are packaged in 689-pin packages which are pin compatible with

544-513: Is expected in 2011. Applications range from high end networking control plane infrastructure, high end storage networking and complex military and industrial devices. In February 2011 Freescale introduced the QorIQ Qonverge platform which is a series of combined CPU and DSP SoC processors targeting wireless infrastructure applications. The PSC913x family chips uses an e500 core based CPU and StarCore SC3850 DSPs will be available in 2011, and

578-463: Is manufactured on a 45 nm process, with e6500 and CS3900 core based 28 nm parts available in 2012 called P4xxx. The QorIQ Advanced Multiprocessing, AMP Series , processors are all based on the multithreaded 64-bit e6500 core with integrated AltiVec SIMD processing units except the lowest end T1 family that uses the older e5500 core. Products will range from single core versions up to parts with 12 cores or more with frequencies ranging all

612-507: Is packaged in 689-pin packages which are pin compatible with the P2 family processors. The P2 series is designed for a wide variety of applications in the networking, telecom, military and industrial markets. It will be available in special high quality parts, with junction tolerances from −40 to 125 °C , especially suited for demanding out doors environments. It is the mid-level platform, with devices ranging from 800 MHz up to 1.2 GHz. It

646-413: Is present in products featuring the e500mc or the e5500. The dual and multi-core devices supports both symmetric and asymmetric multiprocessing , and can run multiple operating systems in parallel. The P1 series is tailored for gateways, Ethernet switches, wireless LAN access points, and general-purpose control applications. It is the entry level platform, ranging from 400 to 800 MHz devices. It

680-821: Is the latest evolution of the QorIQ family, in that features previously provided by DPAA (like compression) may be implemented in software or hardware, depending on the specific chip, but transparent to application programmers. LS-1 and LS-2 are announced to use Cortex A7 , A9 , A15 , A53 and A72 cores. The initial LS-1 series does not include any accelerated packet processing layer, focusing typical power consumption of less than 3W using two Cortex A7 with providing ECC for caches and DDR3/4 at 1000 to 1600 MT/s, dual PCI Express Controllers in x1/x2/x4 operation, SD/MMC, SATA 1/2/3, USB 2/3 with integrated PHY, and virtualized dTSEC Gigabit Ethernet Controllers. LS1 means LS1XXX series (e.g., LS1021A, etc.); LS2 means LS2XXX series. LS2 means

714-426: The e300 core, an enhanced PowerPC 603e core, with 32/32 KiB instruction/data L1 caches. PowerQUICC II Pro is used as networking processors for routers , switches , printers , network-attached storage , wireless access points and DSLAMs . PowerQUICC II Pro processors reaches 677 MHz, and can include a multitude of embedded technologies like USB , PCI , Ethernet and security devices. They also use

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748-478: The EFIKA . See also [ edit ] PowerPC 5000 PowerQUICC References [ edit ] ^ Acura Navigation System Update External links [ edit ] Freescale's mobileGT page Retrieved from " https://en.wikipedia.org/w/index.php?title=MobileGT&oldid=1045826592 " Category : Computing platforms QorIQ QorIQ / ˈ k ɔːr aɪ k j uː /

782-466: The CPU, thus branding this family as PowerQUICC . All processors in the family differ in on-chip features like USB, serial, PCMCIA, ATM and Ethernet controllers and different amount of L1 caches ranging from 1 KiB up to 16 KiB. MPC8xx – All PowerQUICC processors share this common naming scheme. PowerQUICC II was introduced in 1998 and is the direct descendant of PowerPC 603e and the core also goes under

816-596: The P1 family processors. The P3 series is a mid performance networking platform, designed for switching and routing . The P3 family offers a multi-core platform, with support for up to four e500mc cores at frequencies up to 1.5 GHz on the same chip, connected by the CoreNet coherency fabric. The chips include among other integrated functionality, integrated L3 caches , memory controller, multiple I/O-devices such as DUART , GPIO and USB 2.0 , security and encryption engines,

850-410: The P4080, in order to achieve millions of Packet Processing per seconds, the system does not scale with regular software stack because so many cores require a different system design. In order to restore simplicity and still get the highest level of performance, the telecommunication systems are based on a segregation of the cores. Some cores are used for the control plane while some others are used for

884-746: The P4080. The P5 series is based on the high performance 64-bit e5500 core scaling up to 2.5 GHz and allowing numerous auxiliary application processing units as well as multi core operation via the CoreNet fabric. The P5 series processors share the same physical package and are also software backwards compatible with P3 and P4. The P5 processors have 1.3 GHz 64-bit DDR3 memory controllers, 18 SerDes lanes for networking, hardware accelerators for packet handling and scheduling, regular expressions, RAID, security, cryptography and RapidIO. Introduced in June 2010, samples will be available late 2010 and full production

918-470: The PowerQUICC platform. In 2012 Freescale announced ARM -based QorIQ offerings beginning in 2013. The QorIQ brand and the P1, P2 and P4 product families were announced in June 2008. Details of P3 and P5 products were announced in 2010. QorIQ P Series processors were manufactured on a 45 nm fabrication process and was available in the end of 2008 (P1 and P2), mid-2009 (P4) and 2010 (P5). QorIQ T Series

952-418: The e500v2 core, P204x, P30xx and P40xx on the e500mc core, and P50xx on the e5500 core. Features include 32/32 kB data/instruction L1 cache , 36-bit physical memory addressing [appended to the top of the virtual address in the process context, each process is still 32bit], a double precision floating point unit is present on some cores (not all) and support for virtualization through a hypervisor layer

986-736: The 💕 The mobileGT name refers to both a computing platform and an alliance of vendors in the navigation, infotainment and telematics industries. It focuses on automotive , industrial and consumer electronics based on PowerPC and Power ISA processors. The mobileGT Alliance was initiated by Motorola in 2000 and consists today of an array of members from different disciplines like RTOS , middleware , software, graphics, audio, wireless, navigation and development tools. mobileGT solutions can be found in in-car entertainment and informatics systems from many car manufacturers such as BMW , Ford , General Motors , Hyundai and Mercedes-Benz , but can also be found in computing platforms like

1020-547: The name 603e or G2 . The processors still have 16/16 KiB instruction/data L1 caches, and are reaching frequencies up to 450 MHz. These communications processors are used in applications like VoIP systems, telecom switches , cellular base stations and DSLAMs . The PowerQUICC II family of processors are phased out in favour for the more powerful PowerQUICC II Pro line. There's no plans for further development of this core. MPC82xx – All PowerQUICC II processors share this common naming scheme. Introduced in 2004, based on

1054-436: The processors have a built-in encryption module. PowerQUICC will cease development in favor of the software-compatible QorIQ platform featuring all PowerPC e500 based processors, from single core, through multi-core, up to 32 cores. Freescale will keep manufacturing PowerQUICC processors in the foreseeable future for existing customers, but they will help facilitate the transition to QorIQ. MobileGT From Misplaced Pages,

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1088-477: The processors use the older CPM module for the handling network processing offload, some use the newer QUICC Engine (same as in PowerQUICC II Pro), and some do not have a CPM or QUICC Engine at all. Freescale's marketing department nevertheless brand all devices in the 85xx series as being "PowerQUICC III". MPC85xx – All PowerQUICC III processors share this common naming scheme. A trailing "E" signifies that

1122-461: The same chip, connected by the CoreNet coherency fabric. The chips include among other integrated functionality, integrated L3 caches , memory controllers, multiple I/O-devices such as DUART , GPIO and USB 2.0 , security and encryption engines, a queue manager scheduling on-chip events and a SerDes based on-chip high speed network configurable as multiple Gigabit Ethernet, 10 Gigabit Ethernet , RapidIO or PCIe interfaces. The cores are supported by

1156-658: The way up to 2.5 GHz. The processes will be sectioned into five classes according to performance and features, named T1 through T5, and will be manufactured in a 28 nm process beginning in 2012. The T4 family uses the e6500 64-bit dual threaded core. The T2 family uses the e6500 64-bit dual threaded core. The T1 family uses the e5500 64-bit single threaded core at 1.2 to 1.5 GHz with 256 kB L2 cache per core and 256kB shared CoreNet L3 cache. The QorIQ products bring some new challenges in order to design some control planes of telecommunication systems and their data plane . For instance, when 4 or 8 cores are used, such as

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