Misplaced Pages

#689310

89-427: The page table structure used by x86-64 CPUs when operating in long mode further extends the page table hierarchy to four or more levels, extending the virtual address space, and uses additional physical address bits at all levels of the page table, extending the physical address space. It also uses the topmost bit of the 64-bit page table entry as a no-execute or "NX" bit , indicating that code cannot be executed from

178-405: A HPE EPYC -based supercomputer called Frontier is number one. The first ARM-based supercomputer appeared on the list in 2018 and, in recent years, non-CPU architecture co-processors ( GPGPU ) have also played a big role in performance. Intel's Xeon Phi "Knights Corner" coprocessors, which implement a subset of x86-64 with some vector extensions, are also used, along with x86-64 processors, in

267-404: A page frame is the smallest fixed-length contiguous block of physical memory into which memory pages are mapped by the operating system. A transfer of pages between main memory and an auxiliary store, such as a hard disk drive , is referred to as paging or swapping. Computer memory is divided into pages so that information can be found more quickly. The concept is named by analogy to

356-643: A 64-bit OS. A CPU would no longer have legacy mode , and start directly in 64-bit long mode . There will be a way to switch to 5-level paging without going through the unpaged mode. Specific removed features include: Intel believes the change follows logically after the removal of the A20 gate in 2008 and the removal of 16-bit and 32-bit OS support in Intel firmware in 2020. Support for legacy operating systems would be accomplished via hardware-accelerated virtualization and/or ring 0 emulation. Advanced Performance Extensions

445-434: A bit more than 512  GiB of memory (about 0.195% of the 256 TiB virtual space). Intel has implemented a scheme with a 5-level page table , which allows Intel 64 processors to support a 57-bit virtual address space. Further extensions may allow full 64-bit virtual address space and physical memory with 12-bit page table descriptors and 16- or 21-bit memory offsets for 64 KiB and 2 MiB page allocation sizes;

534-766: A completely new design, the Isaiah architecture was built with support for features like the x86-64 instruction set and x86 virtualization which were unavailable on its predecessors, the VIA C7 line, while retaining their encryption extensions. In 2020, through a collaboration between AMD, Intel, Red Hat , and SUSE , three microarchitecture levels (or feature levels) on top of the x86-64 baseline were defined: x86-64-v2, x86-64-v3, and x86-64-v4. These levels define specific features that can be targeted by programmers to provide compile-time optimizations. The features exposed by each level are as follows: baseline for all x86-64 CPUs matches

623-480: A fifth table, the 512-entry page-map level 5 table ; this means that 57 bits of virtual page number are translated, giving a virtual address space of up to 128 PB. In the page table entries, in the original specification, 40 bits of physical page number are implemented. Software can identify via the CPUID flag PAE whether a CPU supports PAE mode or not. A free-of-charge program for Microsoft Windows

712-671: A full specification available in August 2000. As AMD was never invited to be a contributing party for the IA-64 architecture and any kind of licensing seemed unlikely, the AMD64 architecture was positioned by AMD from the beginning as an evolutionary way to add 64-bit computing capabilities to the existing x86 architecture while supporting legacy 32-bit x86 code , as opposed to Intel's approach of creating an entirely new, completely x86-incompatible 64-bit architecture with IA-64. The first AMD64-based processor,

801-485: A given request (a TLB miss ) the page tables must be searched manually (either in hardware or software, depending on the architecture) for the correct mapping. Larger page sizes mean that a TLB cache of the same size can keep track of larger amounts of memory, which avoids the costly TLB misses. Rarely do processes require the use of an exact number of pages. As a result, the last page will likely only be partially full, wasting some amount of memory. Larger page sizes lead to

890-604: A kernel build option. FreeBSD supports PAE in the 4.x series starting with 4.9, in the 5.x series starting with 5.1, and in all 6.x and later releases. Support requires the kernel PAE configuration-option. Loadable kernel modules can only be loaded into a kernel with PAE enabled if the modules were built with PAE enabled; the binary modules in FreeBSD distributions are not built with PAE enabled, and thus cannot be loaded into PAE kernels. Not all drivers support more than 4 GB of physical memory; those drivers won't work correctly on

979-412: A large amount of wasted memory, as more potentially unused portions of memory are loaded into the main memory. Smaller page sizes ensure a closer match to the actual amount of memory required in an allocation. As an example, assume the page size is 1024 B. If a process allocates 1025 B, two pages must be used, resulting in 1023 B of unused space (where one page fully consumes 1024 B and

SECTION 10

#1732858579690

1068-414: A large page table for each process by further dividing the page table up into smaller tables, effectively paging the page table. Since every access to memory must be mapped from virtual to physical address, reading the page table every time can be quite costly. Therefore, a very fast kind of cache, the translation lookaside buffer (TLB), is often used. The TLB is of limited size, and when it cannot satisfy

1157-524: A new 4-level paging mode. With 64-bit mode and the new paging mode, it supports vastly larger amounts of virtual memory and physical memory than was possible on its 32-bit predecessors, allowing programs to store larger amounts of data in memory. x86-64 also expands general-purpose registers to 64-bit, and expands the number of them from 8 (some of which had limited or fixed functionality, e.g. for stack management) to 16 (fully general), and provides numerous other enhancements. Floating-point arithmetic

1246-467: A number of VIA-specific x86 extensions designed to boost efficiency in low-power appliances. It is expected that the Isaiah architecture will be twice as fast in integer performance and four times as fast in floating-point performance as the previous-generation VIA Esther at an equivalent clock speed . Power consumption is also expected to be on par with the previous-generation VIA CPUs, with thermal design power ranging from 5 W to 25 W. Being

1335-709: A reasonable level for small allocations. Starting with the Pentium Pro , and the AMD Athlon , x86 processors support 4 MiB pages (called Page Size Extension ) (2 MiB pages if using PAE ) in addition to their standard 4 KiB pages; newer x86-64 processors, such as AMD 's newer AMD64 processors and Intel 's Westmere and later Xeon processors can use 1 GiB pages in long mode . IA-64 supports as many as eight different page sizes, from 4 KiB up to 256 MiB, and some other architectures have similar features. Larger pages, despite being available in

1424-399: A smaller page size uses more pages, requiring a page table that occupies more space. For example, if a 2 virtual address space is mapped to 4  KiB (2 bytes) pages, the number of virtual pages is 2  = (2  / 2 ). However, if the page size is increased to 32 KiB (2 bytes), only 2 pages are required. A multi-level paging algorithm can decrease the memory cost of allocating

1513-576: A system with PAE. Haiku added initial support for PAE sometime after the R1 Alpha 2 release. With the release of R1 Alpha 3 PAE is now officially supported. ArcaOS has limited support for PAE for the purpose of creating RAM disks above the 4 GB boundary. X86-64 x86-64 (also known as x64 , x86_64 , AMD64 , and Intel 64 ) is a 64-bit version of the x86 instruction set , first announced in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with

1602-469: A system with PAE. OpenBSD has had support for PAE since 2006 with the standard GENERIC i386 kernel. GeNUA mbH supported the initial implementation. Since release 5.0 PAE has had a series of changes, in particular changes to i386 MMU processing for PMAP, see pmap(9). Solaris supports PAE beginning with Solaris version 7. However, third-party drivers used with version 7 which do not specifically include PAE support may operate erratically or fail outright on

1691-443: A system without PAE. Again, this allows data accesses to access physical memory regions beyond the 32-bit range. The entries in the page directory have an additional flag in bit 7, named PS (for page size ). If the system has set this bit to 1 , the page directory entry does not point to a page table but to a single, large 2 MB page ( Page Size Extension ). In all page table formats supported by IA-32 and x86-64 ,

1780-406: A virtual processor running in the desired mode. Since the basic instruction set is the same, there is almost no performance penalty for executing protected mode x86 code. This is unlike Intel's IA-64 , where differences in the underlying instruction set mean that running 32-bit code must be done either in emulation of x86 (making the process slower) or with a dedicated x86 coprocessor. However, on

1869-474: Is a 2023 Intel proposal for new instructions and an additional 16 general-purpose registers. VIA Technologies introduced their first implementation of the x86-64 architecture in 2008 after five years of development by its CPU division, Centaur Technology . Codenamed "Isaiah", the 64-bit architecture was unveiled on January 24, 2008, and launched on May 29 under the VIA Nano brand name. The processor supports

SECTION 20

#1732858579690

1958-536: Is available which will list many processor capabilities, including PAE support. In Linux, commands such as cat /proc/cpuinfo can list the pae flag when present, as well as other tools such as the SYSLINUX Hardware Detection Tool. To run the processor in PAE mode, operating system support is required. To use PAE to access more than 4 GB of RAM, further support is required in the operating system, in

2047-400: Is less apparent. The 32-bit size of the virtual address is not changed, so regular application software continues to use instructions with 32-bit addresses and (in a flat memory model ) is limited to 4 gigabytes of virtual address space. Operating systems supporting this mode use page tables to map the regular 4 GB virtual address space into the physical memory, which, depending on

2136-467: Is made into a submode of legacy mode. It is the submode that 32-bit operating systems and 16-bit protected mode operating systems operate in when running on an x86-64 CPU. Real mode is the initial mode of operation when the processor is initialized, and is a submode of legacy mode. It is backwards compatible with the original Intel 8086 and Intel 8088 processors. Real mode is primarily used today by operating system bootloaders, which are required by

2225-444: Is set), but without PAE, x86 processors use a two-level page translation scheme. Control register CR3 holds the page-aligned physical address of a single 4 KB long page directory . This is divided into 1024 four-byte page directory entries that in turn, if valid, hold the page-aligned physical addresses of page tables , each 4 KB in size. These similarly consist of 1024 four-byte page table entries which, if valid, hold

2314-488: Is supported via mandatory SSE2 -like instructions , and x87 / MMX style registers are generally not used (but still available even in 64-bit mode); instead, a set of 16 vector registers , 128 bits each, is used. (Each register can store one or two double-precision numbers or one to four single-precision numbers, or various integer formats.) In 64-bit mode, instructions are modified to support 64-bit operands and 64-bit addressing mode . The compatibility mode defined in

2403-705: Is the Merom version of the Core 2 processor, which was released on July 27, 2006. None of Intel's earlier notebook CPUs ( Core Duo , Pentium M , Celeron M , Mobile Pentium 4 ) implement Intel 64. Intel's processors implementing the Intel64 architecture include the Pentium 4 F-series/5x1 series, 506, and 516, Celeron D models 3x1, 3x6, 355, 347, 352, 360, and 365 and all later Celerons , all models of Xeon since " Nocona ", all models of Pentium Dual-Core processors since " Merom-2M ",

2492-568: Is used by 64-bit operating systems. Under a 64-bit operating system, 64-bit programs run under 64-bit mode, and 32-bit and 16-bit protected mode applications (that do not need to use either real mode or virtual 8086 mode in order to execute at any time) run under compatibility mode. Real-mode programs and programs that use virtual 8086 mode at any time cannot be run in long mode unless those modes are emulated in software. However, such programs may be started from an operating system running in long mode on processors supporting VT-x or AMD-V by creating

2581-661: The Atom 230, 330, D410, D425, D510, D525, N450, N455, N470, N475, N550, N570, N2600 and N2800, all versions of the Pentium D , Pentium Extreme Edition , Core 2 , Core i9 , Core i7 , Core i5 , and Core i3 processors, and the Xeon Phi 7200 series processors. X86S is a simplification of x86-64 proposed by Intel in May 2023 for their "Intel 64" products. The new architecture would remove support for 16-bit and 32-bit operating systems, while 32-bit programs will still run under

2670-477: The Opteron and Athlon 64 processors, was the first to implement it. This was the first significant addition to the x86 architecture designed by a company other than Intel. Intel was forced to follow suit and introduced a modified NetBurst family which was software-compatible with AMD's specification. VIA Technologies introduced x86-64 in their VIA Isaiah architecture, with the VIA Nano . The x86-64 architecture

2759-523: The Opteron , was released in April 2003. AMD's processors implementing the AMD64 architecture include Opteron , Athlon 64 , Athlon 64 X2 , Athlon 64 FX , Athlon II (followed by "X2", "X3", or "X4" to indicate the number of cores, and XLT models), Turion 64 , Turion 64 X2 , Sempron ("Palermo" E6 stepping and all "Manila" models), Phenom (followed by "X3" or "X4" to indicate the number of cores), Phenom II (followed by "X2", "X3", "X4" or "X6" to indicate

Physical Address Extension - Misplaced Pages Continue

2848-504: The Tianhe-2 supercomputer. The following operating systems and releases support the x86-64 architecture in long mode . Preliminary infrastructure work was started in February 2004 for a x86-64 port. This development later stalled. Development started again during July 2007 and continued during Google Summer of Code 2008 and SoC 2009. The first official release to contain x86-64 support

2937-520: The Windows NT family) take the higher-addressed half of the address space (named kernel space ) for themselves and leave the lower-addressed half ( user space ) for application code, user mode stacks, heaps, and other data regions. The "canonical address" design ensures that every AMD64 compliant implementation has, in effect, two memory halves: the lower half starts at 00000000'00000000 and "grows upwards" as more virtual address bits become available, while

3026-475: The no-execute (NX) or execute-disable (XD) feature, runs in PAE mode in order to allow NX. The NX bit resides in bit 63 of the page table entry and, without PAE, page table entries on 32-bit systems have only 32 bits; therefore PAE mode is required in order to exploit the NX feature. However, "client" versions of 32-bit Windows (Windows XP SP2 and later, Windows Vista, Windows 7) limit physical address space to

3115-485: The page table entry of the x86 architecture is enlarged from 32 to 64 bits. This allows more room for the physical page address, or "page frame number" field, in the page table entry. In the initial implementations of PAE the page frame number field was expanded from 20 to 24 bits. The size of the "byte offset" from the address being translated is still 12 bits, so total physical address size increases from 32 bits to 36 bits (i.e. from 20+12 to 24+12). This increased

3204-566: The "AMD64" nomenclature is used. These are used as synonyms with the x86-64-vX nomenclature and are thus functionally identical. E.g. the Go language documentation or the Fedora linux distribution. All levels include features found in the previous levels. Instruction set extensions not concerned with general-purpose computation, including AES-NI and RDRAND , are excluded from the level requirements. Although nearly identical, there are some differences between

3293-498: The 12 least significant bits of the page table entry are either interpreted by the memory management unit or are reserved for operating system use. In processors that implement the "no-execute" or "execution disable" feature, the most significant bit (bit 63) is the NX bit . The next eleven most significant bits (bits 52 through 62) are reserved for operating system use by both Intel and AMD's architecture specifications. Thus, from 64 bits in

3382-399: The 2.6 series via the hugetlbfs filesystem and without hugetlbfs since 2.6.38. Windows Server 2003 (SP1 and newer), Windows Vista and Windows Server 2008 support huge pages under the name of large pages. Windows 2000 and Windows XP support large pages internally, but do not expose them to applications. Reserving large pages under Windows requires a corresponding right that

3471-405: The 2013 Intel Haswell architecture, excluding Intel-specific instructions Intel Skylake and newer Intel "big" cores (AVX512 enabled models only) AMD Zen 4 and newer AMD cores features match the 2017 Intel Skylake-X architecture, excluding Intel-specific instructions The x86-64 microarchitecture feature levels can also be found as AMD64-v1, AMD64-v2 .. or AMD64_v1 .. in settings where

3560-405: The 64-bit registers. Legacy mode is the mode that the processor is in when it is not in long mode. In this mode, the processor acts like an older x86 processor, and only 16-bit and 32-bit code can be executed. Legacy mode allows for a maximum of 32 bit virtual addressing which limits the virtual address space to 4 GiB. 64-bit programs cannot be run from legacy mode. Protected mode

3649-710: The CPU also support PAE. The Linux kernel supports PAE as a build option and major distributions provide a PAE kernel either as the default or as an option. The NX bit feature requires a kernel built with PAE support. Linux distributions now commonly use a PAE-enabled kernel as the default, a trend that began in 2009. As of 2012 many, including Ubuntu (and derivatives like Xubuntu and Linux Mint ), Red Hat Enterprise Linux 6.0, and CentOS , have stopped distributing non-PAE kernels, thus making PAE-supporting hardware mandatory. Linux distributions that require PAE may refuse to boot on Pentium M family processors because they do not show

Physical Address Extension - Misplaced Pages Continue

3738-553: The OEM market as the Pentium 4, model F. The E0 revision also adds eXecute Disable (XD) (Intel's name for the NX bit ) to Intel 64, and has been included in then current Xeon code-named Irwindale . Intel's official launch of Intel 64 (under the name EM64T at that time) in mainstream desktop processors was the N0 stepping Prescott-2M. The first Intel mobile processor implementing Intel 64

3827-454: The PAE support flag in their CPUID information. This was remedied in a later revision of the "Dothan" core in 2005. It was also available on AMD processors including the AMD Athlon (although the chipsets are limited to 32-bit addressing) and later AMD processor models. When AMD defined their 64-bit extension of the industry standard x86 architecture, AMD64 or x86-64, they also enhanced

3916-530: The PAE support flag in their CPUID information (even though it is supported internally). However, this can be easily bypassed with the forcepae option. Distributions that still provide a non-PAE option, including Debian (and derivatives like LMDE 2 (Linux Mint Debian Edition) ), Slackware , and LXLE , typically do so with "i386", "i486", or "retro" labels. The article Light-weight Linux distribution does list some others, allowing to install Linux onto old computers. FreeBSD and NetBSD also support PAE as

4005-409: The address translation scheme uses PAE but adds a fourth table, the 512-entry page-map level 4 table, and extends the page directory pointer table to 512 entries instead of the original 4 entries it has in protected mode. This means that 48 bits of virtual page number are translated, giving a virtual address space of up to 256 TB. For some processors, a mode can be enabled with

4094-431: The amount of RAM that is usable or supported. Details on this point are given in the " Operating system compatibility and characteristics " section of this article. The architecture has two primary modes of operation: long mode and legacy mode. Long mode is the architecture's intended primary mode of operation; it is a combination of the processor's native 64-bit mode and a combined 32-bit and 16-bit compatibility mode. It

4183-466: The appearance of 64-bit extensions for the x86 architecture enabled 64-bit x86 processors by AMD and Intel to replace most RISC processor architectures previously used in such systems (including PA-RISC , SPARC , Alpha and others), as well as 32-bit x86, even though Intel itself initially tried unsuccessfully to replace x86 with a new incompatible 64-bit architecture in the Itanium processor. As of 2023 ,

4272-652: The appropriate option. According to Microsoft Technical Fellow Mark Russinovich , some drivers were found to be unstable when encountering physical addresses above 4GB. The following table shows the memory limits for 32-bit versions of Microsoft Windows: The original releases of Windows XP and Windows XP SP1 used PAE mode to allow RAM to extend beyond the 4 GB address limit. However, it led to compatibility problems with 3rd party drivers which led Microsoft to remove this capability in Windows XP Service Pack 2. Windows XP SP2 and later, by default, on processors with

4361-430: The architecture allows 16-bit and 32-bit user applications to run unmodified, coexisting with 64-bit applications if the 64-bit operating system supports them. As the full x86 16-bit and 32-bit instruction sets remain implemented in hardware without any intervening emulation, these older executables can run with little or no performance penalty, while newer or modified applications can take advantage of new features of

4450-529: The architecture to configure virtual memory details before transitioning to higher modes. This mode is also used by any operating system that needs to communicate with the system firmware with a traditional BIOS -style interface. Intel 64 is Intel's implementation of x86-64, used and implemented in various processors made by Intel. Historically, AMD has developed and produced processors with instruction sets patterned after Intel's original designs, but with x86-64, roles were reversed: Intel found itself in

4539-660: The associated page. The NX feature is also available in protected mode when these CPUs are running a 32-bit operating system, provided that the operating system enables PAE. PAE was first implemented in the Intel Pentium Pro in 1995, although the accompanying chipsets usually lacked support for the required extra address bits. PAE is supported by the Pentium Pro, Pentium II , Pentium III , and Pentium 4 processors. The first Pentium M family processors ("Banias") introduced in 2003 also support PAE; however, they do not show

SECTION 50

#1732858579690

4628-408: The book is analogous to a page table of a computer file system . Page size is usually determined by the processor architecture. Traditionally, pages in a system had uniform size, such as 4,096 bytes . However, processor designs often allow two or more, sometimes simultaneous, page sizes due to its benefits. There are several points that can factor into choosing the best page size. A system with

4717-525: The chipset, and on the motherboard. Some chipsets do not support physical memory addresses above 4 GB (FFFFFFFF in hexadecimal), and some motherboards simply do not have enough RAM sockets to allow the installation of more than 4 GB of RAM. Nevertheless, even if no more than 4 GB of RAM is available and accessible, a PAE-capable CPU may be run in PAE mode, for example to allow use of the No execute feature. 32-bit versions of Microsoft Windows support PAE if booted with

4806-800: The common capabilities between the 2003 AMD AMD64 and the 2004 Intel EM64T initial implementations in the AMD K8 and the Intel Prescott processor families Intel Nehalem and newer Intel "big" cores Intel (Atom) Silvermont and newer Intel "small" cores AMD Bulldozer and newer AMD "big" cores AMD Jaguar VIA Nano and Eden "C" features match the 2008 Intel Nehalem architecture, excluding Intel-specific instructions Intel Haswell and newer Intel "big" cores (AVX2 enabled models only) Intel (Atom) Gracemont and newer Intel "small" cores AMD Excavator and newer AMD "big" cores QEMU emulation (as of version 7.2) features match

4895-435: The entries of the original scheme, an extra level of hierarchy has been added, so the system register CR3 now points physically to a Page Directory Pointer Table , a short table containing four pointers to page directories. Supporting 64 bit addresses in the page-table is a significant change as this enables two changes to the processor addressing. Firstly, the page table walker, which uses physical addresses to access

4984-781: The first 4 GB for driver compatibility even though these versions do run in PAE mode if NX support is enabled. Windows 8 and later releases will only run on processors which support PAE, in addition to NX and SSE2 . Mac OS X Tiger through Mac OS X Snow Leopard support PAE and the NX bit on IA-32 processors; Snow Leopard was the last version to support IA-32 processors. On x86-64 processors, all versions of macOS use 4-level paging (IA-32e paging rather than PAE) to address memory above 4GB. Mac Pro and Xserve systems can use up to 64 GB of RAM. The Linux kernel includes full PAE-mode support starting with version 2.3.23, in 1999 enabling access of up to 64 GB of memory on 32-bit machines. A PAE-enabled Linux kernel requires that

5073-445: The first implementations of the architecture, only the least significant 48 bits of a virtual address would actually be used in address translation ( page table lookup). In addition, the AMD specification requires that the most significant 16 bits of any virtual address, bits 48 through 63, must be copies of bit 47 (in a manner akin to sign extension ). If this requirement is not met,

5162-546: The full 256 TiB; they were restricted to just 8 TiB of user space and 8 TiB of kernel space. Windows did not support the entire 48-bit address space until Windows 8.1 , which was released in October 2013. The 64-bit addressing mode (" long mode ") is a superset of Physical Address Extensions (PAE); because of this, page sizes may be 4  KiB (2 bytes) or 2  MiB (2 bytes). Long mode also supports page sizes of 1  GiB (2 bytes). Rather than

5251-433: The higher half is "docked" to the top of the address space and grows downwards. Also, enforcing the "canonical form" of addresses by checking the unused address bits prevents their use by the operating system in tagged pointers as flags, privilege markers, etc., as such use could become problematic when the architecture is extended to implement more virtual address bits. The first versions of Windows for x64 did not even use

5340-565: The name Intel 64 for its implementation, paralleling AMD's use of the name AMD64. The first processor to implement Intel 64 was the multi-socket processor Xeon code-named Nocona in June 2004. In contrast, the initial Prescott chips (February 2004) did not enable this feature. Intel subsequently began selling Intel 64-enabled Pentium 4s using the E0 revision of the Prescott core, being sold on

5429-536: The number of cores), FX , Fusion/APU and Ryzen / Epyc . The primary defining characteristic of AMD64 is the availability of 64-bit general-purpose processor registers (for example, rax ), 64-bit integer arithmetic and logical operations, and 64-bit virtual addresses . The designers took the opportunity to make other improvements as well. Notable changes in the 64-bit extensions include: Although virtual addresses are 64 bits wide in 64-bit mode, current implementations (and all chips that are known to be in

SECTION 60

#1732858579690

5518-489: The operating system and the rest of the hardware platform, may be as big as 64 GB. The mapping is typically applied separately for each process , so that the additional RAM is useful even though no single process can access it all simultaneously. Later work associated with AMD's development of x86-64 architecture expanded the theoretical possible size of physical addresses to 52 bits. In protected mode with paging enabled (bit 31, PG , of control register CR0

5607-405: The operating system will automatically use the largest page size possible for a given region of address space. Later work proposed transparent operating system support for using a mix of page sizes for unmodified applications through preemptible reservations, opportunistic promotions, speculative demotions, and fragmentation control. Linux has supported huge pages on several architectures since

5696-420: The other natively. AMD64 (also variously referred to by AMD in their literature and documentation as “AMD 64-bit Technology” and “AMD x86-64 Architecture”) was created as an alternative to the radically different IA-64 architecture designed by Intel and Hewlett-Packard , which was backward-incompatible with IA-32 , the 32-bit version of the x86 architecture. AMD originally announced AMD64 in 1999 with

5785-469: The other only 1 B). When transferring from a rotational disk, much of the delay is caused by seek time, the time it takes to correctly position the read/write heads above the disk platters. Because of this, large sequential transfers are more efficient than several smaller transfers. Transferring the same amount of data from disk to memory often requires less time with larger pages than with smaller pages. Most operating systems allow programs to discover

5874-457: The page size at runtime . This allows programs to use memory more efficiently by aligning allocations to this size and reducing overall internal fragmentation of pages. Unix and POSIX -based systems may use the system function sysconf() , as illustrated in the following example written in the C programming language . In many Unix systems, the command-line utility getconf can be used. For example, getconf PAGESIZE will return

5963-549: The page size in bytes. Win32 -based operating systems, such as those in the Windows 9x and Windows NT families, may use the system function GetSystemInfo() from kernel32.dll . Some instruction set architectures can support multiple page sizes, including pages significantly larger than the standard page size. The available page sizes depend on the instruction set architecture, processor type, and operating (addressing) mode. The operating system selects one or more sizes from

6052-422: The page table and directory, can now access physical addresses greater than the 32-bit physical addresses supported in systems without PAE. From CR3 , the page table walker can access page directories and tables that are beyond the 32-bit range. Secondly, the physical address for the data being accessed (stored in the page table) can be represented as a physical address larger than the 32-bit addresses supported in

6141-568: The page table entry would be expanded to 128 bits to support additional hardware flags for page size and virtual address space size. The operating system can also limit the virtual address space. Details, where applicable, are given in the " Operating system compatibility and characteristics " section. Current AMD64 processors support a physical address space of up to 2 bytes of RAM, or 256  TiB . However, as of 2020 , there were no known x86-64 motherboards that support 256 TiB of RAM. The operating system may place additional limits on

6230-426: The page table entry, 12 low-order and 12 high-order bits have other uses, leaving 40 bits (bits 12 though 51) for the physical page number. Combined with 12 bits of "offset within page" from the linear address, a maximum of 52 bits are available to address physical memory. This allows a maximum RAM configuration of 2 bytes, or 4 petabytes (about 4.5×10 bytes). On x86-64 processors in native long mode ,

6319-405: The page-aligned physical addresses of 4 KB long pages of physical memory (RAM). The entries in the page directory have an additional flag in bit 7, named PS (for page size ). If the system has set this bit to 1 , the page directory entry does not point to a page table but to a single, large 4 MB page ( Page Size Extension ). Enabling PAE (by setting bit 5, PAE , of

6408-414: The pages of a printed book. If a reader wanted to find, for example, the 5,000th word in the book, they could count from the first word. This would be time-consuming. It would be much faster if the reader had a listing of how many words are on each page. From this listing they could determine which page the 5,000th word appears on, and how many words to count on that page. This listing of the words per page of

6497-416: The paging system in " long mode " based on PAE. It supports 64-bit virtual addresses (as of July 2023, 48 bits are implemented on some processors and 57 bits are implemented on others), 52-bit physical addresses, and includes NX bit functionality. When the x86-64 processor is initialized, the PAE feature is required to be enabled before the processor is switched from Legacy Mode to Long Mode. With PAE,

6586-451: The physical memory that is theoretically addressable by the CPU from 4 GB to 64 GB. In the first processors that supported PAE, support for larger physical addresses is evident in their package pinout, with address pin designations going up to A35 instead of stopping at A31. Later processor families use interconnects such as Hypertransport or QuickPath Interconnect , which lack dedicated memory address signals, so this relationship

6675-488: The planning stages) do not allow the entire virtual address space of 2 bytes (16  EiB ) to be used. This would be approximately four billion times the size of the virtual address space on 32-bit machines. Most operating systems and applications will not need such a large address space for the foreseeable future, so implementing such wide virtual addresses would simply increase the complexity and cost of address translation with no real benefit. AMD, therefore, decided that, in

6764-559: The position of adopting the ISA that AMD created as an extension to Intel's own x86 processor line. Intel's project was originally codenamed Yamhill (after the Yamhill River in Oregon's Willamette Valley). After several years of denying its existence, Intel announced at the February 2004 IDF that the project was indeed underway. Intel's chairman at the time, Craig Barrett , admitted that this

6853-405: The processor design to achieve performance improvements. Also, a processor supporting x86-64 still powers on in real mode for full backward compatibility with the 8086 , as x86 processors supporting protected mode have done since the 80286 . The original specification, created by AMD and released in 2000, has been implemented by AMD, Intel , and VIA . The AMD K8 microarchitecture , in

6942-511: The processor will raise an exception. Addresses complying with this rule are referred to as "canonical form." Canonical form addresses run from 0 through 00007FFF'FFFFFFFF, and from FFFF8000'00000000 through FFFFFFFF'FFFFFFFF, for a total of 256  TiB of usable virtual address space. This is still 65,536 times larger than the virtual 4 GiB address space of 32-bit machines. This feature eases later scalability to true 64-bit addressing. Many operating systems (including, but not limited to,

7031-658: The processors used in most contemporary personal computers , are not in common use except in large-scale applications, the applications typically found in large servers and in computational clusters , and in the operating system itself. Commonly, their use requires elevated privileges, cooperation from the application making the large allocation (usually setting a flag to ask the operating system for huge pages), or manual administrator configuration; operating systems commonly, sometimes by design, cannot page them out to disk. However, SGI IRIX has general-purpose support for multiple page sizes. Each individual process can provide hints and

7120-654: The sizes supported by the architecture. Note that not all processors implement all defined larger page sizes. This support for larger pages (known as "huge pages" in Linux , "superpages" in FreeBSD , and "large pages" in Microsoft Windows and IBM AIX terminology) allows for "the best of both worlds", reducing the pressure on the TLB cache (sometimes increasing speed by as much as 15%) for large allocations while still keeping memory usage at

7209-595: The system administrator must grant to the user because large pages cannot be swapped out under Windows. Beginning with version 9, Solaris supports large pages on SPARC and x86. FreeBSD 7.2-RELEASE features superpages. Note that until recently in Linux, applications needed to be modified in order to use huge pages. The 2.6.38 kernel introduced support for transparent use of huge pages. On Linux kernels supporting transparent huge pages, as well as FreeBSD and Solaris , applications take advantage of huge pages automatically, without

7298-417: The system register CR4 ) causes major changes to this scheme. By default, the size of each page remains as 4 KB. Each entry in the page table and page directory becomes 64 bits long (8 bytes), instead of 32 bits, to allow for additional address bits. However, the size of each table does not change, so both table and directory now have only 512 entries. Because this allows only one half of

7387-401: The three-level page table system used by systems in PAE mode, systems running in long mode use four levels of page table: PAE's Page-Directory Pointer Table is extended from four entries to 512, and an additional Page-Map Level 4 (PML4) Table is added, containing 512 entries in 48-bit implementations. A full mapping hierarchy of 4 KiB pages for the whole 48-bit space would take

7476-491: The two instruction sets in the semantics of a few seldom used machine instructions (or situations), which are mainly used for system programming . Compilers generally produce executables (i.e. machine code ) that avoid any differences, at least for ordinary application programs . This is therefore of interest mainly to developers of compilers, operating systems and similar, which must deal with individual and special system instructions. In supercomputers tracked by TOP500 ,

7565-483: The x86 architecture. Work is currently being done to integrate more fully the x86 application binary interface (ABI), in the same manner as the Linux 32-bit ABI compatibility currently works. Page (computing) A page , memory page , or virtual page is a fixed-length contiguous block of virtual memory , described by a single entry in a page table . It is the smallest unit of data for memory management in an operating system that uses virtual memory. Similarly,

7654-410: The x86-64 platform, many x86 applications could benefit from a 64-bit recompile , due to the additional registers in 64-bit code and guaranteed SSE2-based FPU support, which a compiler can use for optimization. However, applications that regularly handle integers wider than 32 bits, such as cryptographic algorithms, will need a rewrite of the code handling the huge integers in order to take advantage of

7743-521: Was one of their worst-kept secrets. Intel's name for this instruction set has changed several times. The name used at the IDF was CT (presumably for Clackamas Technology , another codename from an Oregon river ); within weeks they began referring to it as IA-32e (for IA-32 extensions) and in March 2004 unveiled the "official" name EM64T (Extended Memory 64 Technology). In late 2006 Intel began instead using

7832-471: Was quickly adopted for desktop and laptop personal computers and servers which were commonly configured for 16 GiB ( gibibytes ) of memory or more. It has effectively replaced the discontinued Intel Itanium architecture (formerly IA-64 ), which was originally intended to replace the x86 architecture. x86-64 and Itanium are not compatible on the native instruction set level, and operating systems and applications compiled for one architecture cannot be run on

7921-476: Was version 2.4. FreeBSD first added x86-64 support under the name "amd64" as an experimental architecture in 5.1-RELEASE in June 2003. It was included as a standard distribution architecture as of 5.2-RELEASE in January 2004. Since then, FreeBSD has designated it as a Tier 1 platform. The 6.0-RELEASE version cleaned up some quirks with running x86 executables under amd64, and most drivers work just as they do on

#689310