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17-681: POWER6 was described at the International Solid-State Circuits Conference (ISSCC) in February 2006, and additional details were added at the Microprocessor Forum in October 2006 and at the next ISSCC in February 2007. It was formally announced on May 21, 2007. It was released on June 8, 2007 at speeds of 3.5, 4.2 and 4.7 GHz, but the company has noted prototypes have reached 6 GHz. POWER6 reached first silicon in

34-580: A 5 GHz duty-cycle correction clock distribution network for the processor. In the network, the company implements a copper distribution wire that is 3 μm wide and 1.2 μm thick. The POWER6 design uses dual power supplies, a logic supply in the 0.8-to-1.2 Volt range and an SRAM power supply at about 150-mV higher. The thermal characteristics of POWER6 are similar to that of the POWER5 . Dr Frank Soltis , an IBM chief scientist, said IBM had solved power leakage problems associated with high frequency by using

51-669: A combination of 90 nm and 65 nm parts in the POWER6 design. The slightly enhanced POWER6+ was introduced in April 2009, but had been shipping in Power 560 and 570 systems since October 2008. It added more memory keys for secure memory partition , a feature taken from IBM's mainframe processors . As of 2008, the range of POWER6 systems includes "Express" models (the 520, 550 and 560) and Enterprise models (the 570 and 595). The various system models are designed to serve any sized business. For example,

68-471: A novel decimal floating-point unit. The binary floating-point unit incorporates "many microarchitectures, logic, circuit, latch and integration techniques to achieve [a] 6-cycle, 13- FO4 pipeline", according to a company paper. Unlike the servers from IBM's competitors, the POWER6 has hardware support for IEEE 754 decimal arithmetic and includes the first decimal floating-point unit integrated in silicon. More than 50 new floating point instructions handle

85-649: Is a global forum for presentation of advances in solid-state circuits and Systems-on-a-Chip . The conference is held every year in February at the San Francisco Marriott Marquis in downtown San Francisco . ISSCC is sponsored by IEEE Solid-State Circuits Society. According to The Register , "The ISSCC event is the second event of each new year, following the Consumer Electronics Show , where new PC processors and sundry other computing gadgets are brought to market." Early participants in

102-597: Is supported for blades running AIX, i, and Linux. The BladeCenter E, HT, and T chassis support blades running AIX and Linux but not i. At the SuperComputing 2007 (SC07) conference in Reno a new water-cooled Power 575 was revealed. The 575 is composed of 2U "nodes" each with 32 POWER6 cores at 4.7 GHz with up to 256 GB of RAM. Up to 448 cores can be installed in a single frame. International Solid-State Circuits Conference International Solid-State Circuits Conference

119-578: The University of Pennsylvania . The registration was $ 4 (early registration was $ 3) and 601 people registered. International attendees arrived from Canada, England and Japan. With subsequent conferences came many more international participants with the first international presentation in 1958. By 1965, the number of overseas program committee members increased to 8 and in 1970 the overseas members began meeting separately in both Europe and Japan. Selected members of these regional program committees would attend

136-585: The 520 Express is marketed to small businesses while the Power 595 is marketed for large, multi-environment data centers. The main difference between the Express and Enterprise models is that the latter include Capacity Upgrade on Demand (CUoD) capabilities and hot-pluggable processor and memory "books". IBM also offers four POWER6 based blade servers . Specifications are shown in the table below. All blades support AIX , IBM i , and Linux . The BladeCenter S and H chassis

153-481: The POWER6 still achieves significant performance improvements over the POWER5+ even with unmodified software, according to the lead engineer on the POWER6 project. POWER6 also takes advantage of ViVA-2 , Vi rtual V ector A rchitecture, which enables the combination of several POWER6 nodes to act as a single vector processor . Each core has two integer units , two binary floating-point units , an AltiVec unit, and

170-476: The cache is assigned a specific core, but the other has a fast access to it. The two cores share a 32 MiB L3 cache which is off die, using an 80 GB/s bus. POWER6 can connect to up to 31 other processors using two inter node links (50 GB/s), and supports up to 10 logical partitions per core (up to a limit of 254 per system). There is an interface to a service processor that monitors and adjusts performance and power according to set parameters. IBM also makes use of

187-486: The decimal math and conversions between binary and decimal . This feature was also added to the z10 microprocessor featured in the System z10 . Each core has a 64 KB, four-way set-associative instruction cache and a 64 KB data cache of an eight-way set-associative design with a two-stage pipeline supporting two independent 32-bit reads or one 64-bit write per cycle. Each core has semi-private 4 MiB unified L2 cache , where

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204-532: The final program meeting in America. The name of the 1954 Conference appears in various publications and documents as: "The Transistor Conference", "The Conference on Transistor Circuits", "The Philadelphia Conference", or "The National Conference on Transistor Circuits". The current name "International Solid-State Circuits Conference" was settled by the organizers in 1960. While ISSCC was founded in Philadelphia, in

221-638: The inaugural conference in 1954 belonged to the Institute of Radio Engineers (IRE) Circuit Theory Group and the IRE subcommittee of Transistor Circuits. The conference was held in Philadelphia and local chapters of IRE and American Institute of Electrical Engineers (AIEE) were in attendance. Later on AIEE and IRE would merge to become the present-day IEEE. The first conference consisted of papers from six organizations: Bell Telephone Laboratories , General Electric , RCA , Philco , Massachusetts Institute of Technology and

238-565: The mid-1960s the center of semiconductor development in the United States was shifting west. In 1978, the conference was held on alternate coasts with New York soon substituting for Philadelphia. In 1990, San Francisco became the Conference's permanent home. In 2013, ISSCC celebrated its 60th anniversary and will had several special programs to celebrate 60 years of circuit and SoC innovation. The Technical Program Committee (TPC) in early years

255-605: The middle of 2005, and was bumped to 5.0 GHz in May 2008 with the introduction of the P595. The POWER6 is a dual-core processor. Each core is capable of two-way simultaneous multithreading (SMT). The POWER6 has approximately 790 million transistors and is 341 mm large fabricated on a 65 nm process. A notable difference from POWER5 is that the POWER6 executes instructions in-order instead of out-of-order . This change often requires software to be recompiled for optimal performance, but

272-632: Was extremely fluid in order to deal with the constantly changing topics in the industry. By 1968 the list of subcommittees had settled to Digital, Analog (Linear), Microwave and Other, where the subcommittee members in Other would address the one-of-a-kind papers. In the 80's, the Microwave Subcommittee was dropped from the program as the overlap between the topics and attendees was diminishing. In addition, Digital split into Digital, Memory and Signal Processing subcommittees. In 1992, Emerging Technologies

289-461: Was launched and chartered to seek out the one-of-a-kind applications which may find a home in ISSCC. Today there are 10 subcommittees: Analog, Data Converters, Energy Efficient Digital (EED), High-Performance Digital (HPD), Imagers, MEMs, Medical and Displays (IMMD), Memory, RF, Technology Directions (formerly Emerging Technologies), Wireless and Wireline. ISSCC is a strictly non-profit organization run by

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