The Intel AZ210 , also marketed as XOLO X900 (Intel AZ510) in India, Orange San Diego in the United Kingdom and Megafon Mint in Russia, is a phone manufactured by Taiwanese OEM Gigabyte for Intel.
55-657: It features an Intel Atom processor Z2460 processor running Android 4.0.4 (Ice Cream Sandwich). It is Europe and India's first Android device powered by an Intel processor. The device was first launched in India as the XOLO X900 (Intel AZ510) on 22 April 2012 priced at Rs. 25,000. as of May 2012. Shortly after, the device launched in the United Kingdom & France on June 6, 2012, as the Orange San Diego (Intel AZ210), running on
110-516: A communications subsystem to connect, control, direct and interface between these functional modules. An SoC must have at least one processor core , but typically an SoC has more than one core. Processor cores can be a microcontroller , microprocessor (μP), digital signal processor (DSP) or application-specific instruction set processor (ASIP) core. ASIPs have instruction sets that are customized for an application domain and designed to be more efficient than general-purpose instructions for
165-447: A memory hierarchy and cache hierarchy . In the mobile computing market, this is common, but in many low-power embedded microcontrollers, this is not necessary. Memory technologies for SoCs include read-only memory (ROM), random-access memory (RAM), Electrically Erasable Programmable ROM ( EEPROM ) and flash memory . As in other computer systems, RAM can be subdivided into relatively faster but more expensive static RAM (SRAM) and
220-494: A microcontroller , microprocessor or perhaps several processor cores with peripherals like a GPU , Wi-Fi and cellular network radio modems or one or more coprocessors . Similar to how a microcontroller integrates a microprocessor with peripheral circuits and memory, an SoC can be seen as integrating a microcontroller with even more advanced peripherals . Compared to a multi-chip architecture, an SoC with equivalent functionality will have reduced power consumption as well as
275-653: A netlist describing the design as a physical circuit and its interconnections. These netlists are combined with the glue logic connecting the components to produce the schematic description of the SoC as a circuit which can be printed onto a chip. This process is known as place and route and precedes tape-out in the event that the SoCs are produced as application-specific integrated circuits (ASIC). SoCs must optimize power use , area on die , communication, positioning for locality between modular units and other factors. Optimization
330-399: A semiconductor foundry . This process is called functional verification and it accounts for a significant portion of the time and energy expended in the chip design life cycle , often quoted as 70%. With the growing complexity of chips, hardware verification languages like SystemVerilog , SystemC , e , and OpenVera are being used. Bugs found in the verification stage are reported to
385-465: A 22 nm SoC. It was followed by its platform refresh Moorefield in Q4 2014. While Penwell SoC supports, in addition to Microsoft Windows , both Linux and Android operating systems, Intel has announced that it will not provide support for Linux on Cloverview family of Atom systems-on-a-chip. This announcement has caused strong negative reaction from open source proponents. A few days later Intel issued
440-515: A certain level of computational performance , but power is limited in most SoC environments. SoC designs are optimized to minimize waste heat output on the chip. As with other integrated circuits , heat generated due to high power density are the bottleneck to further miniaturization of components. The power densities of high speed integrated circuits, particularly microprocessors and including SoCs, have become highly uneven. Too much waste heat can damage circuits and erode reliability of
495-527: A chip consists of both the hardware , described in § Structure , and the software controlling the microcontroller, microprocessor or digital signal processor cores, peripherals and interfaces. The design flow for an SoC aims to develop this hardware and software at the same time, also known as architectural co-design. The design flow must also take into account optimizations ( § Optimization goals ) and constraints. Most SoCs are developed from pre-qualified hardware component IP core specifications for
550-1005: A circuit is the integral of power consumed with respect to time, and the average rate of power consumption is the product of current by voltage . Equivalently, by Ohm's law , power is current squared times resistance or voltage squared divided by resistance : P = I V = V 2 R = I 2 R {\displaystyle P=IV={\frac {V^{2}}{R}}={I^{2}}{R}} SoCs are frequently embedded in portable devices such as smartphones , GPS navigation devices , digital watches (including smartwatches ) and netbooks . Customers want long battery lives for mobile computing devices, another reason that power consumption must be minimized in SoCs. Multimedia applications are often executed on these devices, including video games, video streaming , image processing ; all of which have grown in computational complexity in recent years with user demands and expectations for higher- quality multimedia. Computation
605-866: A different processor. For further discussion of multi-processing memory issues, see cache coherence and memory latency . SoCs include external interfaces , typically for communication protocols . These are often based upon industry standards such as USB , Ethernet , USART , SPI , HDMI , I²C , CSI , etc. These interfaces will differ according to the intended application. Wireless networking protocols such as Wi-Fi , Bluetooth , 6LoWPAN and near-field communication may also be supported. When needed, SoCs include analog interfaces including analog-to-digital and digital-to-analog converters , often for signal processing . These may be able to interface with different types of sensors or actuators , including smart transducers . They may interface with application-specific modules or shields. Or they may be internal to
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#1732852638519660-439: A discrete application processor). High-performance SoCs are often paired with dedicated and physically separate memory and secondary storage (such as LPDDR and eUFS or eMMC , respectively) chips that may be layered on top of the SoC in what is known as a package on package (PoP) configuration, or be placed close to the SoC. Additionally, SoCs may use separate wireless modems (especially WWAN modems). An SoC integrates
715-461: A manner independent of time scales, which are typically specified in HDL. Other components can remain software and be compiled and embedded onto soft-core processors included in the SoC as modules in HDL as IP cores . Once the architecture of the SoC has been defined, any new hardware elements are written in an abstract hardware description language termed register transfer level (RTL) which defines
770-486: A power source while needing to maintain autonomous function, and often are limited in power use by a high number of embedded SoCs being networked together in an area. Additionally, energy costs can be high and conserving energy will reduce the total cost of ownership of the SoC. Finally, waste heat from high energy consumption can damage other circuit components if too much heat is dissipated, giving another pragmatic reason to conserve energy. The amount of energy used in
825-464: A smaller semiconductor die area. This comes at the cost of reduced replaceability of components. By definition, SoC designs are fully or nearly fully integrated across different component modules . For these reasons, there has been a general trend towards tighter integration of components in the computer hardware industry , in part due to the influence of SoCs and lessons learned from the mobile and embedded computing markets. SoCs are very common in
880-495: A software integrated development environment . SoCs components are also often designed in high-level programming languages such as C++ , MATLAB or SystemC and converted to RTL designs through high-level synthesis (HLS) tools such as C to HDL or flow to HDL . HLS products called "algorithmic synthesis" allow designers to use C++ to model and synthesize system, circuit, software and verification levels all in one high level language commonly known to computer engineers in
935-429: A specific type of workload. Multiprocessor SoCs have more than one processor core by definition. The ARM architecture is a common choice for SoC processor cores because some ARM-architecture cores are soft processors specified as IP cores . SoCs must have semiconductor memory blocks to perform their computation, as do microcontrollers and other embedded systems . Depending on the application, SoC memory may form
990-463: A statement saying that it has “plans for another version of this platform directed at Linux/Android" The initial Clover Trail platform only supported Microsoft Windows (z27x0 series). The Clover Trail+ platform was later released targeting Google Android (z25x0 series). The last version of Windows 10 to support Cloverview is the Anniversary Update ( version 1607 ) until January 10, 2023 when
1045-458: A supported HDTV. A 3.5 mm audio jack is provided to connect the headset. Frequency Bands: GSM : 850/900/1800/1900, WCDMA / UMTS / HSPA : 850/900/1900/2100, HSPA+ : 850/900/1900/2100. EDGE /GPRS: Class 10. HSPA+ speeds are up to 21 Mbit/s (Download) and up to 5.7 Mbit/s (Upload). The Intel AZ210 originally shipped with Android 2.3.7 ( Gingerbread ) which was updated to Android 4.0.4 Ice Cream Sandwich via OTA . The Russian version
1100-578: Is an integrated circuit that integrates most or all components of a computer or electronic system . These components usually include an on-chip central processing unit (CPU), memory interfaces, input/output devices and interfaces, and secondary storage interfaces, often alongside other components such as radio modems and a graphics processing unit (GPU) – all on a single substrate or microchip. SoCs may contain digital and also analog , mixed-signal and often radio frequency signal processing functions (otherwise it may be considered on
1155-512: Is customised for the intended market and uses SPB Shell 3D launcher and Megafon carrier specific apps. Various mods and tweaks have been created by the Android community at Modaco to improve performance of the device and enable features such as the hidden microSD slot. In June 2012, a television advertisement for the Orange San Diego was broadcast on British television and featured a fast car in computer generated imagery . Richard Noble claimed that
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#17328526385191210-436: Is intended to be used when the device display is off; it consumes power in microwatt range, and can be entered/left in milliseconds. As a result, Intel claims longer standby battery life (up to three weeks for a typical tablet). In May 2011, Intel announced an accelerated roadmap for Atom SoC. The 22 nm Silvermont microarchitecture was scheduled for 2013 release, and release of the 14 nm Airmont microarchitecture
1265-492: Is more demanding as expectations move towards 3D video at high resolution with multiple standards , so SoCs performing multimedia tasks must be computationally capable platform while being low power to run off a standard mobile battery. SoCs are optimized to maximize power efficiency in performance per watt: maximize the performance of the SoC given a budget of power usage. Many applications such as edge computing , distributed processing and ambient intelligence require
1320-780: Is necessarily a design goal of SoCs. If optimization was not necessary, the engineers would use a multi-chip module architecture without accounting for the area use, power consumption or performance of the system to the same extent. Common optimization targets for SoC designs follow, with explanations of each. In general, optimizing any of these quantities may be a hard combinatorial optimization problem, and can indeed be NP-hard fairly easily. Therefore, sophisticated optimization algorithms are often required and it may be practical to use approximation algorithms or heuristics in some cases. Additionally, most SoC designs contain multiple variables to optimize simultaneously , so Pareto efficient solutions are sought after in SoC design. Oftentimes
1375-890: The bottlenecks of bus-based networks. Networks-on-chip have advantages including destination- and application-specific routing , greater power efficiency and reduced possibility of bus contention . Network-on-chip architectures take inspiration from communication protocols like TCP and the Internet protocol suite for on-chip communication, although they typically have fewer network layers . Optimal network-on-chip network architectures are an ongoing area of much research interest. NoC architectures range from traditional distributed computing network topologies such as torus , hypercube , meshes and tree networks to genetic algorithm scheduling to randomized algorithms such as random walks with branching and randomized time to live (TTL). Many SoC researchers consider NoC architectures to be
1430-529: The mobile computing (as in smart devices such as smartphones and tablet computers ) and edge computing markets. In general, there are three distinguishable types of SoCs: SoCs can be applied to any computing task. However, they are typically used in mobile computing such as tablets, smartphones, smartwatches, and netbooks as well as embedded systems and in applications where previously microcontrollers would be used. Where previously only microcontrollers could be used, SoCs are rising to prominence in
1485-580: The Anniedale and Cherryview SoCs. Goldmont-based Atom platforms were to be codenamed Morganfield (smartphones) and Willow Trail (tablets) using the Broxton SoC. The Willow Trail SoC platform was cancelled in April 2016, as Broxton is limited to IoT devices. System on a chip A system on a chip or system-on-chip ( SoC / ˌ ˈ ɛ s oʊ s iː / ; pl. SoCs / ˌ ˈ ɛ s oʊ s iː z / )
1540-487: The FPGA RTL that make signals available for observation. This is used to debug hardware, firmware and software interactions across multiple FPGAs with capabilities similar to a logic analyzer. In parallel, the hardware elements are grouped and passed through a process of logic synthesis , during which performance constraints, such as operational frequency and expected signal delays, are applied. This generates an output known as
1595-762: The Orange network with the Russian variation following on August 22, 2012, which is known as the Megafon Mint. The device uses an Intel Atom SoC Atom Z2460 (codename Medfield), which contains a single-core Intel Atom CPU with HyperThreading running at 1.6 GHz. The device has 1 GB of dedicated RAM, 16 GB of internal storage and a 4.03 inch display with a resolution of WSVGA (1024x600) supporting 16 Million colors covered by Gorilla Glass . The device features stereo speakers of 0.3 Watt output each and dual microphones with an ' Ambient Noise Cancellation ' feature. On
1650-737: The SoC, if needed. Popular time sources are crystal oscillators and phase-locked loops . SoC peripherals including counter -timers, real-time timers and power-on reset generators. SoCs also include voltage regulators and power management circuits. SoCs comprise many execution units . These units must often send data and instructions back and forth. Because of this, all but the most trivial SoCs require communications subsystems . Originally, as with other microcomputer technologies, data bus architectures were used, but recently designs based on sparse intercommunication networks known as networks-on-chip (NoC) have risen to prominence and are forecast to overtake bus architectures for SoC design in
1705-1228: The SoC, such as if an analog sensor is built in to the SoC and its readings must be converted to digital signals for mathematical processing. Digital signal processor (DSP) cores are often included on SoCs. They perform signal processing operations in SoCs for sensors , actuators , data collection , data analysis and multimedia processing. DSP cores typically feature very long instruction word (VLIW) and single instruction, multiple data (SIMD) instruction set architectures , and are therefore highly amenable to exploiting instruction-level parallelism through parallel processing and superscalar execution . SP cores most often feature application-specific instructions, and as such are typically application-specific instruction set processors (ASIP). Such application-specific instructions correspond to dedicated hardware functional units that compute those instructions. Typical DSP instructions include multiply-accumulate , Fast Fourier transform , fused multiply-add , and convolutions . As with other computer systems, SoCs require timing sources to generate clock signals , control execution of SoC functions and provide time context to signal processing applications of
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1760-496: The SoCs as a basis for other small form factor devices (e.g. mini PCs and stick PCs ). In April 2016, Intel announced a major restructuring, including the cancellation of the SoFIA platform. It was reported by many news outlets that Broxton (the final version in the Atom line) was cancelled. In Q1 2014, Intel launched its fully Android compatible smartphone platform Merrifield based on
1815-516: The advertisement and phone were not connected to Noble or Bloodhound SSC. Atom (system on chip) Atom is a system on a chip (SoC) platform designed for smartphones and tablet computers , launched by Intel in 2012. It is a continuation of the partnership announced by Intel and Google on September 13, 2011 to provide support for the Android operating system on Intel x86 processors. This range competes with existing SoCs developed for
1870-860: The back of the device is an 8 MP camera with single LED-flash featuring auto focus and touch focus. A dedicated camera key is provided for easy access. The camera supports up to 8x of digital zoom. It can record videos in full HD 1080p, while the front camera (for video call or video chat) can record videos in HD 720p. The phone supports a burst mode of capturing up to 10 (15 FPS) images per second. Also, it supports Auto, Sports, Portrait, Landscape, Night, Night Portrait, Fireworks, Text modes. The device also includes Accelerometer , Gyroscope , Magnetometer , Ambient light sensor , and Proximity sensor . Intel AZ210 comes loaded with Android Video Player plus doubleTwist . The system supports MPEG4, 3GPP, WMC, H.264, VP8 video codecs and MP3, MIDI, WAV, 3GPP audio codecs natively. It has
1925-401: The capability to play the videos full HD 1080p resolutions at 30 fps. Intel AZ210 supports a number of connectivity features. It has a micro-USB port which runs at USB 2.0 speed for PC connectivity. Bluetooth ver. 2.1. It supports Wi-Fi 802.11 b/g/n. It also features near field communication ( NFC ). The phone supports Wi-Fi tethering . A micro-HDMI port is provided to connect the device to
1980-700: The car was a representation of ThrustSSC , a land speed record car that broke the sound barrier in 1997, and thus these companies had used his intellectual property without permission, putting the future of the successor Bloodhound SSC project in doubt. The Advertising Standards Authority rejected the Bloodhound team's complaint, claiming that intellectual property disputes were not in its remit. According to BBC News technology correspondent Rory Cellan-Jones , Intel and Orange responded that their production team had researched different styles of "superfast vehicles" and developed their own Orange-branded land speed car, and that
2035-427: The circuit behavior, or synthesized into RTL from a high level language through high-level synthesis. These elements are connected together in a hardware description language to create the full SoC design. The logic specified to connect these components and convert between possibly different interfaces provided by different vendors is called glue logic . Chips are verified for validation correctness before being sent to
2090-435: The circuit over time. High temperatures and thermal stress negatively impact reliability, stress migration , decreased mean time between failures , electromigration , wire bonding , metastability and other performance degradation of the SoC over time. In particular, most SoCs are in a small physical area or volume and therefore the effects of waste heat are compounded because there is little room for it to diffuse out of
2145-532: The data throughput of the SoC. This is similar to some device drivers of peripherals on component-based multi-chip module PC architectures. Wire delay is not scalable due to continued miniaturization , system performance does not scale with the number of cores attached, the SoC's operating frequency must decrease with each additional core attached for power to be sustainable, and long wires consume large amounts of electrical power. These challenges are prohibitive to supporting manycore systems on chip. In
2200-676: The designer. Traditionally, engineers have employed simulation acceleration, emulation or prototyping on reprogrammable hardware to verify and debug hardware and software for SoC designs prior to the finalization of the design, known as tape-out . Field-programmable gate arrays (FPGAs) are favored for prototyping SoCs because FPGA prototypes are reprogrammable, allow debugging and are more flexible than application-specific integrated circuits (ASICs). With high capacity and fast compilation time, simulation acceleration and emulation are powerful technologies that provide wide visibility into systems. Both technologies, however, operate slowly, on
2255-804: The embedded systems market. Tighter system integration offers better reliability and mean time between failure , and SoCs offer more advanced functionality and computing power than microcontrollers. Applications include AI acceleration , embedded machine vision , data collection , telemetry , vector processing and ambient intelligence . Often embedded SoCs target the internet of things , multimedia, networking, telecommunications and edge computing markets. Some examples of SoCs for embedded applications include: Mobile computing based SoCs always bundle processors, memories, on-chip caches , wireless networking capabilities and often digital camera hardware and firmware. With increasing memory sizes, high end SoCs will often have no memory and flash storage and instead,
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2310-425: The future of SoC design because they have been shown to efficiently meet power and throughput needs of SoC designs. Current NoC architectures are two-dimensional. 2D IC design has limited floorplanning choices as the number of cores in SoCs increase, so as three-dimensional integrated circuits (3DICs) emerge, SoC designers are looking towards building three-dimensional on-chip networks known as 3DNoCs. A system on
2365-512: The goals of optimizing some of these quantities are directly at odds, further adding complexity to design optimization of SoCs and introducing trade-offs in system design. For broader coverage of trade-offs and requirements analysis , see requirements engineering . SoCs are optimized to minimize the electrical power used to perform the SoC's functions. Most SoCs must use low power. SoC systems often require long battery life (such as smartphones ), can potentially spend months or years without
2420-431: The hardware elements and execution units , collectively "blocks", described above, together with software device drivers that may control their operation. Of particular importance are the protocol stacks that drive industry-standard interfaces like USB . The hardware blocks are put together using computer-aided design tools, specifically electronic design automation tools; the software modules are integrated using
2475-418: The last public security patch KB5022289 was released; later versions of Windows 10 and all versions of Windows 11 cannot be installed. Z2760 Cloverview has introduced two new power states: S0i1 and S0i3. The S0i1 state is intended to be used when the display is on but the user does not actively interact with the device; it consumes power in mW range, and can be entered/left in microseconds. The S0i3 state
2530-482: The late 2010s, a trend of SoCs implementing communications subsystems in terms of a network-like topology instead of bus-based protocols has emerged. A trend towards more processor cores on SoCs has caused on-chip communication efficiency to become one of the key factors in determining the overall system performance and cost. This has led to the emergence of interconnection networks with router -based packet switching known as " networks on chip " (NoCs) to overcome
2585-588: The memory and flash memory will be placed right next to, or above ( package on package ), the SoC. Some examples of mobile computing SoCs include: In 1992, Acorn Computers produced the A3010, A3020 and A4000 range of personal computers with the ARM250 SoC. It combined the original Acorn ARM2 processor with a memory controller (MEMC), video controller (VIDC), and I/O controller (IOC). In previous Acorn ARM -powered computers, these were four discrete chips. The ARM7500 chip
2640-471: The near future. Historically, a shared global computer bus typically connected the different components, also called "blocks" of the SoC. A very common bus for SoC communications is ARM's royalty-free Advanced Microcontroller Bus Architecture ( AMBA ) standard. Direct memory access controllers route data directly between external interfaces and SoC memory, bypassing the CPU or control unit , thereby increasing
2695-430: The order of MHz, which may be significantly slower – up to 100 times slower – than the SoC's operating frequency. Acceleration and emulation boxes are also very large and expensive at over US$ 1 million. FPGA prototypes, in contrast, use FPGAs directly to enable engineers to validate and test at, or close to, a system's full operating frequency with real-world stimuli. Tools such as Certus are used to insert probes in
2750-633: The risk of catastrophic failure . Due to increased transistor densities as length scales get smaller, each process generation produces more heat output than the last. Compounding this problem, SoC architectures are usually heterogeneous, creating spatially inhomogeneous heat fluxes , which cannot be effectively mitigated by uniform passive cooling . SoCs are optimized to maximize computational and communications throughput . SoCs are optimized to minimize latency for some or all of their functions. This can be accomplished by laying out elements with proper proximity and locality to each-other to minimize
2805-458: The slower but cheaper dynamic RAM (DRAM). When an SoC has a cache hierarchy, SRAM will usually be used to implement processor registers and cores' built-in caches whereas DRAM will be used for main memory . "Main memory" may be specific to a single processor (which can be multi-core ) when the SoC has multiple processors , in this case it is distributed memory and must be sent via § Intermodule communication on-chip to be accessed by
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#17328526385192860-455: The smartphone and tablet market from companies such as Texas Instruments , Nvidia , Qualcomm and Samsung . Unlike these companies, which use ARM -based CPUs designed from the beginning to consume very low power, Intel has adapted the x86-based Intel Atom line of CPU developed for low power usage in netbooks, to even lower power usage. Since April 2012, several manufacturers have released Intel Atom-based tablets and phones as well as using
2915-420: The system. Because of high transistor counts on modern devices, oftentimes a layout of sufficient throughput and high transistor density is physically realizable from fabrication processes but would result in unacceptably high amounts of heat in the circuit's volume. These thermal effects force SoC and other chip designers to apply conservative design margins , creating less performant devices to mitigate
2970-554: Was scheduled for 2014. It has been reported that Silvermont-based Atom SoCs will be codenamed Tangier (Merrifield smartphones), Valleyview (Bay Trail tablets), will be available in single-, dual- and quad-core versions, and Valleyview will include Intel's 7th generation GPU, allowing for 4–7× improvement over existing Atom GPUs. Other upcoming Silvermont-based Atom SoCs include Rangeley and Avoton (part of Edisonville platform). Airmont-based Atom platforms will be codenamed Moorefield (smartphones) and Cherry Trail (tablets) using
3025-709: Was their second-generation SoC, based on the ARM700, VIDC20 and IOMD controllers, and was widely licensed in embedded devices such as set-top-boxes, as well as later Acorn personal computers. Tablet and laptop manufacturers have learned lessons from embedded systems and smartphone markets about reduced power consumption, better performance and reliability from tighter integration of hardware and firmware modules , and LTE and other wireless network communications integrated on chip (integrated network interface controllers ). An SoC consists of hardware functional units , including microprocessors that run software code , as well as
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