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103-579: The 8086 -based N5200 , released in 1981, was the first computer to use the NEC μPD7220 High-Performance Graphics Display Controller. The better-known PC-9800 series , released a year later by the different division, had a similar architecture to the original N5200 and used many of the same components. The most significant differences between the two were that the PC-9801 had slightly lower vertical screen resolution, graphics were standard instead of optional (still using

206-768: A computer terminal for ACOS mainframe platforms. It was developed by the Terminal Units Division who developed computer terminals for mainframes, but the PC-98 was developed by the Small Systems Division who developed standalone enterprise systems. The position of the N5200 is similar to IBM 3270 PC , but there is significant difference that the N5200 didn't offer the PC-98 compatibility instead it had own software library. As of 1982, both CP/M-86 and MS-DOS lacked task switching and an ISAM support, so NEC developed

309-440: A clock/calendar chip, parallel printer and RS-232 serial interfaces, and one or two built-in 8" floppy diskette drives supporting both single-sided single-density (243 KB) and double-sided double-density (1 MB) formats. (An external 10 MB hard disk drive was also available.) The detachable keyboard had 86 keys (including the numeric keypad ) and an additional 22 function keys. A built-in 12" monochrome or 8-colour display

412-430: A fully static CMOS version for battery powered devices, manufactured using Intel's CHMOS processes. The original chip measured 33 mm² and minimum feature size was 3.2 μm. The MUL and DIV instructions were very slow due to being microcoded so x86 programmers usually just used the bit shift instructions for multiplying and dividing instead. The 8086 was die-shrunk to 2 μm in 1981; this version also corrected

515-430: A fully static CMOS version for battery powered devices, manufactured using Intel's CHMOS processes. The original chip measured 33 mm² and minimum feature size was 3.2 μm. The MUL and DIV instructions were very slow due to being microcoded so x86 programmers usually just used the bit shift instructions for multiplying and dividing instead. The 8086 was die-shrunk to 2 μm in 1981; this version also corrected

618-445: A functional computer, in part due to it being packaged in a small 18-pin "memory package", which ruled out the use of a separate address bus (Intel was primarily a DRAM manufacturer at the time). Two years later, Intel launched the 8080 , employing the new 40-pin DIL packages originally developed for calculator ICs to enable a separate address bus. It had an extended instruction set that

721-400: A functional computer, in part due to it being packaged in a small 18-pin "memory package", which ruled out the use of a separate address bus (Intel was primarily a DRAM manufacturer at the time). Two years later, Intel launched the 8080 , employing the new 40-pin DIL packages originally developed for calculator ICs to enable a separate address bus. It had an extended instruction set that

824-501: A limited-edition CPU celebrating the 40th anniversary of the Intel 8086, called the Intel Core i7-8086K . In 1972, Intel launched the 8008 , Intel's first 8-bit microprocessor. It implemented an instruction set designed by Datapoint Corporation with programmable CRT terminals in mind, which also proved to be fairly general-purpose. The device needed several additional ICs to produce

927-401: A limited-edition CPU celebrating the 40th anniversary of the Intel 8086, called the Intel Core i7-8086K . In 1972, Intel launched the 8008 , Intel's first 8-bit microprocessor. It implemented an instruction set designed by Datapoint Corporation with programmable CRT terminals in mind, which also proved to be fairly general-purpose. The device needed several additional ICs to produce

1030-436: A mathematical coprocessor to add hardware/microcode-based floating-point performance. The Intel 8087 was the standard math coprocessor for the 8086 and 8088, operating on 80-bit numbers. Manufacturers like Cyrix (8087-compatible) and Weitek ( not 8087-compatible) eventually came up with high-performance floating-point coprocessors that competed with the 8087. The clock frequency was originally limited to 5 MHz, but

1133-436: A mathematical coprocessor to add hardware/microcode-based floating-point performance. The Intel 8087 was the standard math coprocessor for the 8086 and 8088, operating on 80-bit numbers. Manufacturers like Cyrix (8087-compatible) and Weitek ( not 8087-compatible) eventually came up with high-performance floating-point coprocessors that competed with the 8087. The clock frequency was originally limited to 5 MHz, but

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1236-411: A program small enough to fit in one segment. Far pointers are 32-bit segment:offset pairs resolving to 20-bit external addresses. Some compilers also support huge pointers, which are like far pointers except that pointer arithmetic on a huge pointer treats it as a linear 20-bit pointer, while pointer arithmetic on a far pointer wraps around within its 16-bit offset without touching the segment part of

1339-411: A program small enough to fit in one segment. Far pointers are 32-bit segment:offset pairs resolving to 20-bit external addresses. Some compilers also support huge pointers, which are like far pointers except that pointer arithmetic on a huge pointer treats it as a linear 20-bit pointer, while pointer arithmetic on a far pointer wraps around within its 16-bit offset without touching the segment part of

1442-437: A proprietary operating system for the N5200, called PTOS. PTOS was ported to the PC-98 in the early 1990s, and the N5200 computer line was absorbed. The first APC was released in 1982 at $ 3,298 for a single-floppy monochrome system or $ 4,998 for a dual-floppy color system. It used a 16-bit NEC μPD 8086 CPU with 128 KB of RAM (expandable to 256 KB), 8 KB of ROM , and 4 KB of battery-backed CMOS RAM ,

1545-399: A second μPD7220) and it used 5.25" floppy drives instead of 8". The APC IV , despite sharing the series name, was an ordinary IBM PC/AT compatible and not compatible with the earlier APC models. The N5200 is a series of personal computers released in 1981. The APC is a version of the N5200 that was sold outside Japan. Although its computer architecture is very similar to the PC-98, it

1648-591: A single ALU cycle (instead of two, via internal carry, as in the 8080 and 8085), speeding up such instructions considerably. Combined with orthogonalizations of operations versus operand types and addressing modes , as well as other enhancements, this made the performance gain over the 8080 or 8085 fairly significant, despite cases where the older chips may be faster (see below). As can be seen from these tables, operations on registers and immediates were fast (between 2 and 4 cycles), while memory-operand instructions and jumps were quite slow; jumps took more cycles than on

1751-591: A single ALU cycle (instead of two, via internal carry, as in the 8080 and 8085), speeding up such instructions considerably. Combined with orthogonalizations of operations versus operand types and addressing modes , as well as other enhancements, this made the performance gain over the 8080 or 8085 fairly significant, despite cases where the older chips may be faster (see below). As can be seen from these tables, operations on registers and immediates were fast (between 2 and 4 cycles), while memory-operand instructions and jumps were quite slow; jumps took more cycles than on

1854-457: A single segment, just as in most 8-bit based processors, and can be used to build .com files for instance. Precompiled libraries often come in several versions compiled for different memory models. According to Morse et al.,. the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16 MB physical address space. However, as this would have forced segments to begin on 256-byte boundaries, and 1 MB

1957-457: A single segment, just as in most 8-bit based processors, and can be used to build .com files for instance. Precompiled libraries often come in several versions compiled for different memory models. According to Morse et al.,. the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16 MB physical address space. However, as this would have forced segments to begin on 256-byte boundaries, and 1 MB

2060-423: A small program (less than 64 KB) can be loaded starting at a fixed offset (such as 0000) in its own segment, avoiding the need for relocation , with at most 15 bytes of alignment waste. Compilers for the 8086 family commonly support two types of pointer , near and far . Near pointers are 16-bit offsets implicitly associated with the program's code or data segment and so can be used only within parts of

2163-423: A small program (less than 64 KB) can be loaded starting at a fixed offset (such as 0000) in its own segment, avoiding the need for relocation , with at most 15 bytes of alignment waste. Compilers for the 8086 family commonly support two types of pointer , near and far . Near pointers are 16-bit offsets implicitly associated with the program's code or data segment and so can be used only within parts of

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2266-422: A stack register bug in the original 3.5 μm chips. Later 1.5 μm and CMOS variants were outsourced to other manufacturers and not developed in-house. The architecture was defined by Stephen P. Morse with some help from Bruce Ravenel (the architect of the 8087) in refining the final revisions. Logic designer Jim McKevitt and John Bayliss were the lead engineers of the hardware-level development team and Bill Pohlman

2369-422: A stack register bug in the original 3.5 μm chips. Later 1.5 μm and CMOS variants were outsourced to other manufacturers and not developed in-house. The architecture was defined by Stephen P. Morse with some help from Bruce Ravenel (the architect of the 8087) in refining the final revisions. Logic designer Jim McKevitt and John Bayliss were the lead engineers of the hardware-level development team and Bill Pohlman

2472-635: Is source-compatible (not binary compatible ) with the 8008 and also included some 16-bit instructions to make programming easier. The 8080 device was eventually replaced by the depletion-load -based 8085 (1977), which used a single +5 V power supply instead of the three different operating voltages of earlier chips. Other well known 8-bit microprocessors that emerged during these years are Motorola 6800 (1974), General Instrument PIC16X (1975), MOS Technology 6502 (1975), Zilog Z80 (1976), and Motorola 6809 (1978). The 8086 project started in May 1976 and

2575-589: Is source-compatible (not binary compatible ) with the 8008 and also included some 16-bit instructions to make programming easier. The 8080 device was eventually replaced by the depletion-load -based 8085 (1977), which used a single +5 V power supply instead of the three different operating voltages of earlier chips. Other well known 8-bit microprocessors that emerged during these years are Motorola 6800 (1974), General Instrument PIC16X (1975), MOS Technology 6502 (1975), Zilog Z80 (1976), and Motorola 6809 (1978). The 8086 project started in May 1976 and

2678-495: Is a 16-bit microprocessor chip designed by Intel between early 1976 and June 8, 1978, when it was released. The Intel 8088 , released July 1, 1979, is a slightly modified chip with an external 8-bit data bus (allowing the use of cheaper and fewer supporting ICs ), and is notable as the processor used in the original IBM PC design. The 8086 gave rise to the x86 architecture, which eventually became Intel's most successful line of processors. On June 5, 2018, Intel released

2781-495: Is a 16-bit microprocessor chip designed by Intel between early 1976 and June 8, 1978, when it was released. The Intel 8088 , released July 1, 1979, is a slightly modified chip with an external 8-bit data bus (allowing the use of cheaper and fewer supporting ICs ), and is notable as the processor used in the original IBM PC design. The 8086 gave rise to the x86 architecture, which eventually became Intel's most successful line of processors. On June 5, 2018, Intel released

2884-672: Is assumed, specifically, that the DS and ES segments address the same region of memory. Although partly shadowed by other design choices in this particular chip, the multiplexed address and data buses limit performance slightly; transfers of 16-bit or 8-bit quantities are done in a four-clock memory access cycle, which is faster on 16-bit, although slower on 8-bit quantities, compared to many contemporary 8-bit based CPUs. As instructions vary from one to six bytes, fetch and execution are made concurrent and decoupled into separate units (as it remains in today's x86 processors): The bus interface unit feeds

2987-627: Is assumed, specifically, that the DS and ES segments address the same region of memory. Although partly shadowed by other design choices in this particular chip, the multiplexed address and data buses limit performance slightly; transfers of 16-bit or 8-bit quantities are done in a four-clock memory access cycle, which is faster on 16-bit, although slower on 8-bit quantities, compared to many contemporary 8-bit based CPUs. As instructions vary from one to six bytes, fetch and execution are made concurrent and decoupled into separate units (as it remains in today's x86 processors): The bus interface unit feeds

3090-450: Is copied one byte (8-bit character) at a time. The example code uses the BP (base pointer) register to establish a call frame , an area on the stack that contains all of the parameters and local variables for the execution of the subroutine. This kind of calling convention supports reentrant and recursive code and has been used by Algol-like languages since the late 1950s. A flat memory model

3193-405: Is copied one byte (8-bit character) at a time. The example code uses the BP (base pointer) register to establish a call frame , an area on the stack that contains all of the parameters and local variables for the execution of the subroutine. This kind of calling convention supports reentrant and recursive code and has been used by Algol-like languages since the late 1950s. A flat memory model

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3296-425: Is limited to 64 KB, simply because internal address/index registers are only 16 bits wide. Programming over 64 KB memory boundaries involves adjusting the segment registers (see below); this difficulty existed until the 80386 architecture introduced wider (32-bit) registers (the memory management hardware in the 80286 did not help in this regard, as its registers are still only 16 bits wide). Some of

3399-425: Is limited to 64 KB, simply because internal address/index registers are only 16 bits wide. Programming over 64 KB memory boundaries involves adjusting the segment registers (see below); this difficulty existed until the 80386 architecture introduced wider (32-bit) registers (the memory management hardware in the 80286 did not help in this regard, as its registers are still only 16 bits wide). Some of

3502-476: Is supported in hardware ; 16-bit words are pushed onto the stack, and the top of the stack is pointed to by SS:SP. There are 256  interrupts , which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the return addresses . The 8086 has 64 K of 8-bit (or alternatively 32 K of 16-bit word) I/O port space. The 8086 has a 16-bit flags register . Nine of these condition code flags are active, and indicate

3605-476: Is supported in hardware ; 16-bit words are pushed onto the stack, and the top of the stack is pointed to by SS:SP. There are 256  interrupts , which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the return addresses . The 8086 has 64 K of 8-bit (or alternatively 32 K of 16-bit word) I/O port space. The 8086 has a 16-bit flags register . Nine of these condition code flags are active, and indicate

3708-515: Is that the 8086 also introduced some new instructions (not present in the 8080 and 8085) to better support stack-based high-level programming languages such as Pascal and PL/M ; some of the more useful instructions are push mem-op , and ret size , supporting the "Pascal calling convention " directly. (Several others, such as push   immed and enter , were added in the subsequent 80186, 80286, and 80386 processors.) A 64 KB (one segment) stack growing towards lower addresses

3811-515: Is that the 8086 also introduced some new instructions (not present in the 8080 and 8085) to better support stack-based high-level programming languages such as Pascal and PL/M ; some of the more useful instructions are push mem-op , and ret size , supporting the "Pascal calling convention " directly. (Several others, such as push   immed and enter , were added in the subsequent 80186, 80286, and 80386 processors.) A 64 KB (one segment) stack growing towards lower addresses

3914-475: The ALGOL -family of languages, including Pascal and PL/M . According to principal architect Stephen P. Morse , this was a result of a more software-centric approach. Other enhancements included microcode instructions for the multiply and divide assembly language instructions. Designers also anticipated coprocessors , such as 8087 and 8089 , so the bus structure was designed to be flexible. The first revision of

4017-428: The ALGOL -family of languages, including Pascal and PL/M . According to principal architect Stephen P. Morse , this was a result of a more software-centric approach. Other enhancements included microcode instructions for the multiply and divide assembly language instructions. Designers also anticipated coprocessors , such as 8087 and 8089 , so the bus structure was designed to be flexible. The first revision of

4120-594: The Unix derivative, PC-UX . Later, MS DOS 3.1 was released for the APC. The APC III was not fully compatible with the IBM-PC, either on a hardware level (although some parts were compatible), or a software level (although again, some software was compatible). Later on NEC released the SLE card, or 'Software Library Expander', that was essentially an IBM PC on an expansion board, although graphics

4223-488: The "16-bit microprocessor" identity of the 8086. A 20-bit external address bus provides a 1  MiB physical address space (2 = 1,048,576 x 1 byte ). This address space is addressed by means of internal memory "segmentation". The data bus is multiplexed with the address bus in order to fit all of the control lines into a standard 40-pin dual in-line package . It provides a 16-bit I/O address bus, supporting 64  KB of separate I/O space. The maximum linear address space

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4326-488: The "16-bit microprocessor" identity of the 8086. A 20-bit external address bus provides a 1  MiB physical address space (2 = 1,048,576 x 1 byte ). This address space is addressed by means of internal memory "segmentation". The data bus is multiplexed with the address bus in order to fit all of the control lines into a standard 40-pin dual in-line package . It provides a 16-bit I/O address bus, supporting 64  KB of separate I/O space. The maximum linear address space

4429-540: The 1998–1999 Lunar Prospector . For the packaging, the Intel 8086 was available both in ceramic and plastic DIP packages. Compatible—and, in many cases, enhanced—versions were manufactured by Fujitsu , Harris / Intersil , OKI , Siemens , Texas Instruments , NEC , Mitsubishi , and AMD . For example, the NEC V20 and NEC V30 pair were hardware-compatible with the 8088 and 8086 even though NEC made original Intel clones μPD8088D and μPD8086D respectively, but incorporated

4532-491: The 1998–1999 Lunar Prospector . For the packaging, the Intel 8086 was available both in ceramic and plastic DIP packages. Compatible—and, in many cases, enhanced—versions were manufactured by Fujitsu , Harris / Intersil , OKI , Siemens , Texas Instruments , NEC , Mitsubishi , and AMD . For example, the NEC V20 and NEC V30 pair were hardware-compatible with the 8088 and 8086 even though NEC made original Intel clones μPD8088D and μPD8086D respectively, but incorporated

4635-464: The 8086 itself. The 8086 has eight more-or-less general 16-bit registers (including the stack pointer but excluding the instruction pointer, flag register and segment registers). Four of them, AX, BX, CX, DX, can also be accessed as 8-bit register pairs (see figure) while the other four, SI, DI, BP, SP, are 16-bit only. Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that

4738-464: The 8086 itself. The 8086 has eight more-or-less general 16-bit registers (including the stack pointer but excluding the instruction pointer, flag register and segment registers). Four of them, AX, BX, CX, DX, can also be accessed as 8-bit register pairs (see figure) while the other four, SI, DI, BP, SP, are 16-bit only. Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that

4841-610: The 8086 through both industrial espionage and reverse engineering . The resulting chip, K1810VM86 , was binary and pin-compatible with the 8086. i8086 and i8088 were respectively the cores of the Soviet-made PC-compatible EC1831 and EC1832 desktops. (EC1831 is the EC identification of IZOT 1036C and EC1832 is the EC identification of IZOT 1037C, developed and manufactured in Bulgaria. EC stands for Единая Система.) However,

4944-439: The 8086 through both industrial espionage and reverse engineering . The resulting chip, K1810VM86 , was binary and pin-compatible with the 8086. i8086 and i8088 were respectively the cores of the Soviet-made PC-compatible EC1831 and EC1832 desktops. (EC1831 is the EC identification of IZOT 1036C and EC1832 is the EC identification of IZOT 1037C, developed and manufactured in Bulgaria. EC stands for Единая Система.) However,

5047-584: The EC1831 computer (IZOT 1036C) had significant hardware differences from the IBM PC prototype. The EC1831 was the first PC-compatible computer with dynamic bus sizing (US Pat. No 4,831,514). Later some of the EC1831 principles were adopted in PS/2 (US Pat. No 5,548,786) and some other machines (UK Patent Application, Publication No. GB-A-2211325, Published June 28, 1989). Intel 8086 The 8086 (also called iAPX 86 )

5150-498: The address. To avoid the need to specify near and far on numerous pointers, data structures, and functions, compilers also support "memory models" which specify default pointer sizes. The tiny (max 64K), small (max 128K), compact (data > 64K), medium (code > 64K), large (code,data > 64K), and huge (individual arrays > 64K) models cover practical combinations of near, far, and huge pointers for code and data. The tiny model means that code and data are shared in

5253-498: The address. To avoid the need to specify near and far on numerous pointers, data structures, and functions, compilers also support "memory models" which specify default pointer sizes. The tiny (max 64K), small (max 128K), compact (data > 64K), medium (code > 64K), large (code,data > 64K), and huge (individual arrays > 64K) models cover practical combinations of near, far, and huge pointers for code and data. The tiny model means that code and data are shared in

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5356-440: The colour (or, for monochrome screens, whether it was highlighted or not) and any mix of reverse video, blinking, over-bar , under-bar and blanked (not displayed). The optional graphics board adds a second μPD7220 graphics controller with up to 512 KB memory displaying 640 × 494 graphics that overlay the text screen output. (This is higher than the resolution of the user-addressable text screen because graphics can overlay

5459-457: The control pins, which carry essential signals for all external operations, have more than one function depending upon whether the device is operated in min or max mode. The former mode is intended for small single-processor systems, while the latter is for medium or large systems using more than one processor (a kind of multiprocessor mode). Maximum mode is required when using an 8087 or 8089 coprocessor. The voltage on pin 33 (MN/ MX ) determines

5562-457: The control pins, which carry essential signals for all external operations, have more than one function depending upon whether the device is operated in min or max mode. The former mode is intended for small single-processor systems, while the latter is for medium or large systems using more than one processor (a kind of multiprocessor mode). Maximum mode is required when using an 8087 or 8089 coprocessor. The voltage on pin 33 (MN/ MX ) determines

5665-483: The current state of the processor: Carry flag (CF), Parity flag (PF), Auxiliary carry flag (AF), Zero flag (ZF), Sign flag (SF), Trap flag (TF), Interrupt flag (IF), Direction flag (DF), and Overflow flag (OF). Also referred to as the status word, the layout of the flags register is as follows: There are also four 16-bit segment registers (see figure) that allow the 8086 CPU to access one megabyte of memory in an unusual way. Rather than concatenating

5768-483: The current state of the processor: Carry flag (CF), Parity flag (PF), Auxiliary carry flag (AF), Zero flag (ZF), Sign flag (SF), Trap flag (TF), Interrupt flag (IF), Direction flag (DF), and Overflow flag (OF). Also referred to as the status word, the layout of the flags register is as follows: There are also four 16-bit segment registers (see figure) that allow the 8086 CPU to access one megabyte of memory in an unusual way. Rather than concatenating

5871-467: The display was stuck at 640 × 400 with 8 colors. The NEC APC series supported a proprietary NEC APC character set and user-definable fonts in text mode. The expansion bus supported 16-bit-wide data and 20-bit-wide address capability. By comparison, the original IBM supported an 8-bit data bus with 20-bit address, which was later revised to 16 data bits and 24 address bits in the PC AT . The motherboard

5974-489: The equivalence of different segment:offset pairs. In practice the use of "huge" pointers and similar mechanisms was widespread and the flat 32-bit addressing made possible with the 32-bit offset registers in the 80386 eventually extended the limited addressing range in a more general way. The instruction stream is fetched from memory as words and is addressed internally by the processor to the byte level as necessary. An instruction stream queuing mechanism allows up to 6 bytes of

6077-489: The equivalence of different segment:offset pairs. In practice the use of "huge" pointers and similar mechanisms was widespread and the flat 32-bit addressing made possible with the 32-bit offset registers in the 80386 eventually extended the limited addressing range in a more general way. The instruction stream is fetched from memory as words and is addressed internally by the processor to the byte level as necessary. An instruction stream queuing mechanism allows up to 6 bytes of

6180-403: The exterior case, as was required for the IBM PC. The entire computer could be disassembled to functional blocks (e.g.: expansion card cage, power supply, disk drive cage) with removal of a few easy access screws. Other components didn't even need a screwdriver, except for the outer case, by using robust plastic clips. The disk cage could be further disassembled if required. As with the IBM PC,

6283-420: The instruction set and high level architecture was ready after about three months, and as almost no CAD tools were used, four engineers and 12 layout people were simultaneously working on the chip. The 8086 took a little more than two years from idea to working product, which was considered fast for a complex design in the 1970s. The 8086 was sequenced using a mixture of random logic and microcode and

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6386-420: The instruction set and high level architecture was ready after about three months, and as almost no CAD tools were used, four engineers and 12 layout people were simultaneously working on the chip. The 8086 took a little more than two years from idea to working product, which was considered fast for a complex design in the 1970s. The 8086 was sequenced using a mixture of random logic and microcode and

6489-513: The instruction set of the 80186 along with some (but not all) of the 80186 speed enhancements, providing a drop-in capability to upgrade both instruction set and processing speed without manufacturers having to modify their designs. Such relatively simple and low-power 8086-compatible processors in CMOS are still used in embedded systems. The electronics industry of the Soviet Union was able to replicate

6592-412: The instruction set of the 80186 along with some (but not all) of the 80186 speed enhancements, providing a drop-in capability to upgrade both instruction set and processing speed without manufacturers having to modify their designs. Such relatively simple and low-power 8086-compatible processors in CMOS are still used in embedded systems. The electronics industry of the Soviet Union was able to replicate

6695-507: The instruction stream to be queued while waiting for decoding and execution. The queue acts as a First-In-First-Out (FIFO) buffer, from which the Execution Unit (EU) extracts instruction bytes as required. Whenever there is space for at least two bytes in the queue, the BIU will attempt a word fetch memory cycle. If the queue is empty (following a branch instruction, for example), the first byte into

6798-404: The instruction stream to be queued while waiting for decoding and execution. The queue acts as a First-In-First-Out (FIFO) buffer, from which the Execution Unit (EU) extracts instruction bytes as required. Whenever there is space for at least two bytes in the queue, the BIU will attempt a word fetch memory cycle. If the queue is empty (following a branch instruction, for example), the first byte into

6901-452: The instruction stream to the execution unit through a 6-byte prefetch queue (a form of loosely coupled pipelining ), speeding up operations on registers and immediates , while memory operations became slower (four years later, this performance problem was fixed with the 80186 and 80286 ). However, the full (instead of partial) 16-bit architecture with a full width ALU meant that 16-bit arithmetic instructions could now be performed with

7004-452: The instruction stream to the execution unit through a 6-byte prefetch queue (a form of loosely coupled pipelining ), speeding up operations on registers and immediates , while memory operations became slower (four years later, this performance problem was fixed with the 80186 and 80286 ). However, the full (instead of partial) 16-bit architecture with a full width ALU meant that 16-bit arithmetic instructions could now be performed with

7107-511: The last versions in HMOS were specified for 10 MHz. HMOS-III and CMOS versions were manufactured for a long time (at least a while into the 1990s) for embedded systems , although its successor, the 80186 / 80188 (which includes some on-chip peripherals), has been more popular for embedded use. The 80C86, the CMOS version of the 8086, was used in the GRiDPad , Toshiba T1200 , HP 110 , and finally

7210-416: The last versions in HMOS were specified for 10 MHz. HMOS-III and CMOS versions were manufactured for a long time (at least a while into the 1990s) for embedded systems , although its successor, the 80186 / 80188 (which includes some on-chip peripherals), has been more popular for embedded use. The 80C86, the CMOS version of the 8086, was used in the GRiDPad , Toshiba T1200 , HP 110 , and finally

7313-620: The manager for the project. The legacy of the 8086 is enduring in the basic instruction set of today's personal computers and servers; the 8086 also lent its last two digits to later extended versions of the design, such as the Intel 286 and the Intel 386 , all of which eventually became known as the x86 family. (Another reference is that the PCI Vendor ID for Intel devices is 8086 h .) All internal registers, as well as internal and external data buses, are 16 bits wide, which firmly established

7416-518: The manager for the project. The legacy of the 8086 is enduring in the basic instruction set of today's personal computers and servers; the 8086 also lent its last two digits to later extended versions of the design, such as the Intel 286 and the Intel 386 , all of which eventually became known as the x86 family. (Another reference is that the PCI Vendor ID for Intel devices is 8086 h .) All internal registers, as well as internal and external data buses, are 16 bits wide, which firmly established

7519-710: The maximum usable memory was 640 KB (the address range of the Intel 8088 and 8086 is 1 MB). The APC came with 128 KB standard. RS-232 serial, Centronics parallel and video interfaces were built onto the motherboard, whereas expansion cards were required for almost every function of an IBM PC except for the CPU, BIOS and built-in RAM. Maximum display capabilities were a text mode of 80 × 25 characters (with four planes) and/or graphics at 640 × 400 pixels (with two planes). Either text, graphics, or graphics with text overlay were software selectable. The base one bit-per-pixel

7622-399: The mode. Changing the state of pin 33 changes the function of certain other pins, most of which have to do with how the CPU handles the (local) bus. The mode is usually hardwired into the circuit and therefore cannot be changed by software. The workings of these modes are described in terms of timing diagrams in Intel datasheets and manuals. In minimum mode, all control signals are generated by

7725-399: The mode. Changing the state of pin 33 changes the function of certain other pins, most of which have to do with how the CPU handles the (local) bus. The mode is usually hardwired into the circuit and therefore cannot be changed by software. The workings of these modes are described in terms of timing diagrams in Intel datasheets and manuals. In minimum mode, all control signals are generated by

7828-640: The original NEC APC, all the NEC APC models utilized the Intel 8086 processor, unlike the IBM PC and clones. The unit was physically smaller than an IBM-PC. The compact case included two 5 1 ⁄ 4 " half-height disks (two floppies or one floppy and one hard disk), and space for standard options ( hard disk controller , additional video memory). Special options (including additional system memory) required using expansion slots, of which four were available. C-bus expansion cards (PCBs) could be inserted without removal of

7931-476: The queue immediately becomes available to the EU. Small programs could ignore the segmentation and just use plain 16-bit addressing. This allows 8-bit software to be quite easily ported to the 8086. The authors of most DOS implementations took advantage of this by providing an Application Programming Interface very similar to CP/M as well as including the simple .com executable file format, identical to CP/M. This

8034-431: The queue immediately becomes available to the EU. Small programs could ignore the segmentation and just use plain 16-bit addressing. This allows 8-bit software to be quite easily ported to the 8086. The authors of most DOS implementations took advantage of this by providing an Application Programming Interface very similar to CP/M as well as including the simple .com executable file format, identical to CP/M. This

8137-441: The result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the destination , while the other operand, the source , can be either register or immediate . A single memory location can also often be used as both source and destination which, among other factors, further contributes to a code density comparable to (and often better than) most eight-bit machines at

8240-441: The result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the destination , while the other operand, the source , can be either register or immediate . A single memory location can also often be used as both source and destination which, among other factors, further contributes to a code density comparable to (and often better than) most eight-bit machines at

8343-546: The segment register with the address register, as in most processors whose address space exceeds their register size, the 8086 shifts the 16-bit segment only four bits left before adding it to the 16-bit offset (16×segment + offset), therefore producing a 20-bit external (or effective or physical) address from the 32-bit segment:offset pair. As a result, each external address can be referred to by 2 = 4096 different segment:offset pairs. Although considered complicated and cumbersome by many programmers, this scheme also has advantages;

8446-546: The segment register with the address register, as in most processors whose address space exceeds their register size, the 8086 shifts the 16-bit segment only four bits left before adding it to the 16-bit offset (16×segment + offset), therefore producing a 20-bit external (or effective or physical) address from the 32-bit segment:offset pair. As a result, each external address can be referred to by 2 = 4096 different segment:offset pairs. Although considered complicated and cumbersome by many programmers, this scheme also has advantages;

8549-551: The simple 8080 and 8085 , and the 8088 (used in the IBM PC) was additionally hampered by its narrower bus. The reasons why most memory related instructions were slow were threefold: However, memory access performance was drastically enhanced with Intel's next generation of 8086 family CPUs. The 80186 and 80286 both had dedicated address calculation hardware, saving many cycles, and the 80286 also had separate (non-multiplexed) address and data buses. The 8086/8088 could be connected to

8652-502: The simple 8080 and 8085 , and the 8088 (used in the IBM PC) was additionally hampered by its narrower bus. The reasons why most memory related instructions were slow were threefold: However, memory access performance was drastically enhanced with Intel's next generation of 8086 family CPUs. The 80186 and 80286 both had dedicated address calculation hardware, saving many cycles, and the 80286 also had separate (non-multiplexed) address and data buses. The 8086/8088 could be connected to

8755-452: The status line as well.) The graphics controller allows panning the screen over the display memory, zooming, independent scrolling of different screen areas and other graphics functions. A light pen can be used for input. Operating systems included CP/M-86 and MS-DOS . The APC III (Advanced Personal Computer) was released by NEC in 1984. An update on the NEC APC II, which replaced

8858-448: The time such as the PDP-11 , VAX , 68000 , 32016 , etc. On the other hand, being more regular than the rather minimalistic but ubiquitous 8-bit microprocessors such as the 6502 , 6800 , 6809 , 8085 , MCS-48 , 8051 , and other contemporary accumulator-based machines, it is significantly easier to construct an efficient code generator for the 8086 architecture. Another factor for this

8961-400: The time such as the PDP-11 , VAX , 68000 , 32016 , etc. On the other hand, being more regular than the rather minimalistic but ubiquitous 8-bit microprocessors such as the 6502 , 6800 , 6809 , 8085 , MCS-48 , 8051 , and other contemporary accumulator-based machines, it is significantly easier to construct an efficient code generator for the 8086 architecture. Another factor for this

9064-411: The time. The degree of generality of most registers is much greater than in the 8080 or 8085. However, 8086 registers were more specialized than in most contemporary minicomputers and are also used implicitly by some instructions. While perfectly sensible for the assembly programmer, this makes register allocation for compilers more complicated compared to more orthogonal 16-bit and 32-bit processors of

9167-411: The time. The degree of generality of most registers is much greater than in the 8080 or 8085. However, 8086 registers were more specialized than in most contemporary minicomputers and are also used implicitly by some instructions. While perfectly sensible for the assembly programmer, this makes register allocation for compilers more complicated compared to more orthogonal 16-bit and 32-bit processors of

9270-436: Was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there were not enough pins available on a low cost 40-pin package for the additional four address bus pins. In principle, the address space of the x86 series could have been extended in later processors by increasing the shift value, as long as applications obtained their segments from the operating system and did not make assumptions about

9373-436: Was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there were not enough pins available on a low cost 40-pin package for the additional four address bus pins. In principle, the address space of the x86 series could have been extended in later processors by increasing the shift value, as long as applications obtained their segments from the operating system and did not make assumptions about

9476-403: Was designed to allow easy addition of an 8087 math co-processor . Most Australian units were shipped with 720 KB floppy disk drives (80 track, double density), although specifications imply the drives were only 360 KB (40 track, DD). 360 KB disks were readable and writeable by 'double-stepping' the 720 KB drives. Users could also purchase a hard disk expansion option. This

9579-421: Was developed and marketed in a different way. At that time, NEC was a vertical integrated company as seen in other big Japanese companies, and intended to open new business. The management allowed a few divisions to start a new computer business, so each divisions developed own computer systems for different markets. The N5200 was marketed as a personal computer which could be used as both a standalone computer and

9682-429: Was driven by an NEC μPD7220 display controller generating an 80 × 25 character display. An additional line at the top of the screen displayed status information. Each character was displayed in an 8 × 19 dot cell (giving 640 × 475 screen resolution) and could be one of 250 predefined 7 × 11 glyphs from ROM or 256 user-defined 8 × 16 glyphs from RAM. Each character cell also had an attribute byte indicating

9785-527: Was easily upgradeable to three bits per pixel (taking the graphics mode from monochrome to either eight colours or eight shades of grey). The computer was capable of running monochrome (or grey) through an NTSC TV monitor, although this was not recommended (text reduced to 40 × 20 , graphics to 640 × 200 ). Monochrome (usually green) or color screens were usually included in the price. The APC III's 'on-board' video controller meant that upgrades (other than internally mounted video memory) could not be achieved, and

9888-399: Was implemented using depletion-load nMOS circuitry with approximately 20,000 active transistors (29,000 counting all ROM and PLA sites). It was soon moved to a new refined nMOS manufacturing process called HMOS (for High performance MOS) that Intel originally developed for manufacturing of fast static RAM products. This was followed by HMOS-II, HMOS-III versions, and, eventually,

9991-399: Was implemented using depletion-load nMOS circuitry with approximately 20,000 active transistors (29,000 counting all ROM and PLA sites). It was soon moved to a new refined nMOS manufacturing process called HMOS (for High performance MOS) that Intel originally developed for manufacturing of fast static RAM products. This was followed by HMOS-II, HMOS-III versions, and, eventually,

10094-423: Was important when the 8086 and MS-DOS were new, because it allowed many existing CP/M (and other) applications to be quickly made available, greatly easing acceptance of the new platform. The following 8086 assembly source code is for a subroutine named _strtolower that copies a null-terminated ASCIIZ character string from one location to another, converting all alphabetic characters to lower case. The string

10197-423: Was important when the 8086 and MS-DOS were new, because it allowed many existing CP/M (and other) applications to be quickly made available, greatly easing acceptance of the new platform. The following 8086 assembly source code is for a subroutine named _strtolower that copies a null-terminated ASCIIZ character string from one location to another, converting all alphabetic characters to lower case. The string

10300-484: Was initially limited to the 10 MB ST-506 hard disks. This capacity could be increased to 20 MB (but no higher) after upgrading to MS-DOS 3.1 . The hard disk controller was only configured to operate a single internal hard disk. An external hard disk expansion port was available, so you could have two floppies and an external hard drive, or one floppy with an internal hard drive. Shipped standard with MS-DOS 2.11, other operating systems were available, such as

10403-523: Was limited to CGA only, quite a step down from the native graphics. The earlier penetration of the market saw PC clones adopt the IBM PC architecture. In the export markets, NEC fell into line with the 16-bit IBM-AT architecture and did not pursue the APC-III architecture any further. The APC IV, released in 1986, was an IBM PC/AT clone that was not designed to be compatible with previous APC models. Intel 8086 The 8086 (also called iAPX 86 )

10506-699: Was originally intended as a temporary substitute for the ambitious and delayed iAPX 432 project. It was an attempt to draw attention from the less-delayed 16-bit and 32-bit processors of other manufacturers — Motorola , Zilog , and National Semiconductor . Whereas the 8086 was a 16-bit microprocessor, it used the same microarchitecture as Intel's 8-bit microprocessors (8008, 8080, and 8085). This allowed assembly language programs written in 8-bit to seamlessly migrate . New instructions and features — such as signed integers, base+offset addressing, and self-repeating operations — were added. Instructions were added to assist source code compilation of nested functions in

10609-699: Was originally intended as a temporary substitute for the ambitious and delayed iAPX 432 project. It was an attempt to draw attention from the less-delayed 16-bit and 32-bit processors of other manufacturers — Motorola , Zilog , and National Semiconductor . Whereas the 8086 was a 16-bit microprocessor, it used the same microarchitecture as Intel's 8-bit microprocessors (8008, 8080, and 8085). This allowed assembly language programs written in 8-bit to seamlessly migrate . New instructions and features — such as signed integers, base+offset addressing, and self-repeating operations — were added. Instructions were added to assist source code compilation of nested functions in

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