Misplaced Pages

#774225

69-485: In June 2007, AMD released low-voltage variants of their low-end 65 nm Athlon 64 X2 , named " Athlon X2 ". The Athlon X2 processors feature reduced thermal design power (TDP) of 45 Watt (W). The name was also used for K10 based budget CPUs with two cores deactivated. The primary benefit of dual-core processors (like the Athlon 64 X2) over single-core processors is their ability to process more software threads at

138-443: A multi-core processor ), in which case the copy in the cache may become out-of-date or stale. Alternatively, when a CPU in a multiprocessor system updates data in the cache, copies of data in caches associated with other CPUs become stale. Communication protocols between the cache managers that keep the data consistent are known as cache coherence protocols. Cache performance measurement has become important in recent times where

207-423: A 96 KiB L1 instruction cache (and 128 KiB L1 data cache), and Intel Ice Lake -based processors from 2018, having 48 KiB L1 data cache and 48 KiB L1 instruction cache. In 2020, some Intel Atom CPUs (with up to 24 cores) have (multiple of) 4.5 MiB and 15 MiB cache sizes. Data is transferred between memory and cache in blocks of fixed size, called cache lines or cache blocks . When

276-422: A cache line is copied from memory into the cache, a cache entry is created. The cache entry will include the copied data as well as the requested memory location (called a tag). When the processor needs to read or write a location in memory, it first checks for a corresponding entry in the cache. The cache checks for the contents of the requested memory location in any cache lines that might contain that address. If

345-431: A common virtual address space. A program executes by calculating, comparing, reading and writing to addresses of its virtual address space, rather than addresses of physical address space, making programs simpler and thus easier to write. Virtual memory requires the processor to translate virtual addresses generated by the program into physical addresses in main memory. The portion of the processor that does this translation

414-429: A direct-mapped cache, closer to the miss rate of a fully associative cache. Comparing with a direct-mapped cache, a set associative cache has a reduced number of bits for its cache set index that maps to a cache set, where multiple ways or blocks stays, such as 2 blocks for a 2-way set associative cache and 4 blocks for a 4-way set associative cache. Comparing with a direct mapped cache, the unused cache index bits become

483-456: A great degree, and some situations benefit from it far more than others. Some programs are currently written for only one thread, and thus cannot use the processing power of a second core. Programs often written with multiple threads and able to use two cores include many music and video encoding applications, and especially professional rendering programs. High TLP applications currently correspond to server and workstation situations more than

552-400: A location in the main memory, the processor checks whether the data from that location is already in the cache. If so, the processor will read from or write to the cache instead of the much slower main memory. Many modern desktop , server , and industrial CPUs have at least three independent levels of caches (L1, L2 and L3) and different types of caches: Early examples of CPU caches include

621-523: A mapping table held in core memory before every programmed access to main memory. With no caches, and with the mapping table memory running at the same speed as main memory this effectively cut the speed of memory access in half. Two early machines that used a page table in main memory for mapping, the IBM System/360 Model 67 and the GE 645 , both had a small associative memory as a cache for accesses to

690-505: A part of the tag bits. For example, a 2-way set associative cache contributes 1 bit to the tag and a 4-way set associative cache contributes 2 bits to the tag. The basic idea of the multicolumn cache is to use the set index to map to a cache set as a conventional set associative cache does, and to use the added tag bits to index a way in the set. For example, in a 4-way set associative cache, the two bits are used to index way 00, way 01, way 10, and way 11, respectively. This double cache indexing

759-474: A shared dual-channel memory controller/north bridge and additional control logic. The initial versions are based on the E stepping model of the Athlon 64 and, depending on the model, have either 512 or 1024 KB of L2 cache per core. The Athlon 64 X2 can decode instructions for Streaming SIMD Extensions 3 ( SSE3 ), except those few specific to Intel's architecture. The first Athlon 64 X2 CPUs were released in May 2005, in

SECTION 10

#1732854704775

828-512: A small production number of the Socket-AM2 Athlon 64 X2 with 1 MB L2 cache per core, known as 4000+, 4400+, 4800+, and 5200+. The Athlon 64 X2 with 512 KB per core, known as 3800+, 4200+, 4600+, and 5000+, were produced in far greater numbers. The introduction of the F3 stepping then saw several models with 1 MB L2 cache per core as production refinements resulted in an increased yield. '64'

897-407: A small production number of the Socket-AM2 Athlon 64 X2 with 1 MB L2 cache per core, known as 4000+, 4400+, 4800+, and 5200+. The Athlon 64 X2 with 512 KB per core, known as 3800+, 4200+, 4600+, and 5000+, were produced in far greater numbers. The introduction of the F3 stepping then saw several models with 1 MB L2 cache per core as production refinements resulted in an increased yield. '64'

966-416: A smaller, faster memory, located closer to a processor core , which stores copies of the data from frequently used main memory locations . Most CPUs have a hierarchy of multiple cache levels (L1, L2, often L3, and rarely even L4), with different instruction-specific and data-specific caches at level 1. The cache memory is typically implemented with static random-access memory (SRAM), in modern CPUs by far

1035-402: Is a failed attempt to read or write a piece of data in the cache, which results in a main memory access with much longer latency. There are three kinds of cache misses: instruction read miss, data read miss, and data write miss. Cache read misses from an instruction cache generally cause the largest delay, because the processor, or at least the thread of execution , has to wait (stall) until

1104-399: Is called a "major location mapping", and its latency is equivalent to a direct-mapped access. Extensive experiments in multicolumn cache design shows that the hit ratio to major locations is as high as 90%. If cache mapping conflicts with a cache block in the major location, the existing cache block will be moved to another cache way in the same set, which is called "selected location". Because

1173-471: Is called a stall. As CPUs become faster compared to main memory, stalls due to cache misses displace more potential computation; modern CPUs can execute hundreds of instructions in the time taken to fetch a single cache line from main memory. Various techniques have been employed to keep the CPU busy during this time, including out-of-order execution in which the CPU attempts to execute independent instructions after

1242-517: Is crucial to CPU performance, and so most modern level-1 caches are virtually indexed, which at least allows the MMU's TLB lookup to proceed in parallel with fetching the data from the cache RAM. But virtual indexing is not the best choice for all cache levels. The cost of dealing with virtual aliases grows with cache size, and as a result most level-2 and larger caches are physically indexed. Caches have historically used both virtual and physical addresses for

1311-594: Is equal to the number of cache blocks divided by the number of ways of associativity, what leads to 128 / 4 = 32 sets, and hence 2  = 32 different indices. There are 2  = 64 possible offsets. Since the CPU address is 32 bits wide, this implies 32 − 5 − 6 = 21 bits for the tag field. The original Pentium 4 processor also had an eight-way set associative L2 integrated cache 256 KiB in size, with 128-byte cache blocks. This implies 32 − 8 − 7 = 17 bits for

1380-496: Is extra latency from computing the hash function. Additionally, when it comes time to load a new line and evict an old line, it may be difficult to determine which existing line was least recently used, because the new line conflicts with data at different indexes in each way; LRU tracking for non-skewed caches is usually done on a per-set basis. Nevertheless, skewed-associative caches have major advantages over conventional set-associative ones. A true set-associative cache tests all

1449-399: Is free to choose any entry in the cache to hold the copy, the cache is called fully associative . At the other extreme, if each entry in the main memory can go in just one place in the cache, the cache is direct-mapped . Many caches implement a compromise in which each entry in the main memory can go to any one of N places in the cache, and are described as N-way set associative. For example,

SECTION 20

#1732854704775

1518-623: Is generally dynamic random-access memory (DRAM) on a separate die or chip, rather than static random-access memory (SRAM). An exception to this is when eDRAM is used for all levels of cache, down to L1. Historically L1 was also on a separate die, however bigger die sizes have allowed integration of it as well as other cache levels, with the possible exception of the last level. Each extra level of cache tends to be bigger and optimized differently. Caches (like for RAM historically) have generally been sized in powers of: 2, 4, 8, 16 etc. KiB ; when up to MiB sizes (i.e. for larger non-L1), very early on

1587-489: Is known as the memory management unit (MMU). The fast path through the MMU can perform those translations stored in the translation lookaside buffer (TLB), which is a cache of mappings from the operating system's page table , segment table, or both. For the purposes of the present discussion, there are three important features of address translation: One early virtual memory system, the IBM M44/44X , required an access to

1656-471: Is no perfect method to choose among the variety of replacement policies available. One popular replacement policy, least-recently used (LRU), replaces the least recently accessed entry. Marking some memory ranges as non-cacheable can improve performance, by avoiding caching of memory regions that are rarely re-accessed. This avoids the overhead of loading something into the cache without having any reuse. Cache entries may also be disabled or locked depending on

1725-454: Is written back to the main memory only when that data is evicted from the cache. For this reason, a read miss in a write-back cache may sometimes require two memory accesses to service: one to first write the dirty location to main memory, and then another to read the new location from memory. Also, a write to a main memory location that is not yet mapped in a write-back cache may evict an already dirty location, thereby freeing that cache space for

1794-555: The Atlas 2 and the IBM System/360 Model 85 in the 1960s. The first CPUs that used a cache had only one level of cache; unlike later level 1 cache, it was not split into L1d (for data) and L1i (for instructions). Split L1 cache started in 1976 with the IBM 801 CPU, became mainstream in the late 1980s, and in 1997 entered the embedded CPU market with the ARMv5TE. In 2015, even sub-dollar SoCs split

1863-430: The skewed cache , where the index for way 0 is direct, as above, but the index for way 1 is formed with a hash function . A good hash function has the property that addresses which conflict with the direct mapping tend not to conflict when mapped with the hash function, and so it is less likely that a program will suffer from an unexpectedly large number of conflict misses due to a pathological access pattern. The downside

1932-598: The 65 nm Athlon 64 with 77.2 mm and 122 million transistors. As a result, a larger area of silicon must be defect free . These size requirements necessitate a more complex fabrication process , which further adds to the production of fewer functional processors per single silicon wafer. This lower yield makes the X2 more expensive to produce than the single-core processor. In the middle of June 2006 AMD stated that they would no longer make any non-FX Athlon 64 or Athlon 64 X2 models with 1 MB L2 caches. This led to only

2001-550: The 65 nm Athlon 64 with 77.2 mm and 122 million transistors. As a result, a larger area of silicon must be defect free . These size requirements necessitate a more complex fabrication process , which further adds to the production of fewer functional processors per single silicon wafer. This lower yield makes the X2 more expensive to produce than the single-core processor. In the middle of June 2006 AMD stated that they would no longer make any non-FX Athlon 64 or Athlon 64 X2 models with 1 MB L2 caches. This led to only

2070-461: The Athlon 64 X2) over single-core processors is their ability to process more software threads at the same time. The ability of processors to execute multiple threads simultaneously is called thread-level parallelism (TLP). By placing two cores on the same die, the X2 effectively doubles the TLP over a single-core Athlon 64 of the same speed. The need for TLP processing ability depends on the situation to

2139-446: The L1 cache. They also have L2 caches and, for larger processors, L3 caches as well. The L2 cache is usually not split, and acts as a common repository for the already split L1 cache. Every core of a multi-core processor has a dedicated L1 cache and is usually not shared between the cores. The L2 cache, and higher-level caches, may be shared between the cores. L4 cache is currently uncommon, and

Athlon 64 X2 - Misplaced Pages Continue

2208-409: The advantages of a direct-mapped cache is that it allows simple and fast speculation . Once the address has been computed, the one cache index which might have a copy of that location in memory is known. That cache entry can be read, and the processor can continue to work with that data before it finishes checking that the tag actually matches the requested address. The idea of having the processor use

2277-488: The associativity of their caches in low-power states, which acts as a power-saving measure. In order of worse but simple to better but complex: In this cache organization, each location in the main memory can go in only one entry in the cache. Therefore, a direct-mapped cache can also be called a "one-way set associative" cache. It does not have a placement policy as such, since there is no choice of which cache entry's contents to evict. This means that if two locations map to

2346-404: The cache do not have to include that part of the main memory address which is implied by the cache memory's index. Since the cache tags have fewer bits, they require fewer transistors, take less space on the processor circuit board or on the microprocessor chip, and can be read and compared faster. Also LRU algorithm is especially simple since only one bit needs to be stored for each pair. One of

2415-409: The cache performance, reducing the miss rate becomes one of the necessary steps among other steps. Decreasing the access time to the cache also gives a boost to its performance and helps with optimization. The time taken to fetch one cache line from memory (read latency due to a cache miss) matters because the CPU will run out of work while waiting for the cache line. When a CPU reaches this state, it

2484-583: The cache. (The tag, flag and error correction code bits are not included in the size, although they do affect the physical area of a cache.) An effective memory address which goes along with the cache line (memory block) is split ( MSB to LSB ) into the tag, the index and the block offset. The index describes which cache set that the data has been put in. The index length is ⌈ log 2 ⁡ ( s ) ⌉ {\displaystyle \lceil \log _{2}(s)\rceil } bits for s cache sets. The block offset specifies

2553-455: The cached data before the tag match completes can be applied to associative caches as well. A subset of the tag, called a hint , can be used to pick just one of the possible cache entries mapping to the requested address. The entry selected by the hint can then be used in parallel with checking the full tag. The hint technique works best when used in the context of address translation, as explained below. Other schemes have been suggested, such as

2622-575: The consumer segment of the market, the X2 improves on the performance of the original Athlon 64, especially for multi-threaded software. Having two cores, the Athlon 64 X2 has an increased number of transistors . The 1 MB L2 cache 90 nm Athlon 64 X2 processor is 219 mm in size with 243 million transistors whereas its 1 MB L2 cache 90 nm Athlon 64 counterpart is 103.1 mm and has 164 million transistors. The 65 nm Athlon 64 X2 with only 512 KB L2 per Core reduced this to 118 mm with 221 million transistors compared to

2691-408: The contents of the cache. To make room for the new entry on a cache miss, the cache may have to evict one of the existing entries. The heuristic it uses to choose the entry to evict is called the replacement policy. The fundamental problem with any replacement policy is that it must predict which existing cache entry is least likely to be used in the future. Predicting the future is difficult, so there

2760-471: The context. If data is written to the cache, at some point it must also be written to main memory; the timing of this write is known as the write policy. In a write-through cache, every write to the cache causes a write to main memory. Alternatively, in a write-back or copy-back cache, writes are not immediately mirrored to the main memory, and the cache instead tracks which locations have been written over, marking them as dirty . The data in these locations

2829-490: The current set (the set has been retrieved by index) to see if this set contains the requested address. If it does, a cache hit occurs. The tag length in bits is as follows: Some authors refer to the block offset as simply the "offset" or the "displacement". The original Pentium 4 processor had a four-way set associative L1 data cache of 8  KiB in size, with 64-byte cache blocks. Hence, there are 8 KiB / 64 = 128 cache blocks. The number of sets

Athlon 64 X2 - Misplaced Pages Continue

2898-434: The desired data within the stored data block within the cache row. Typically the effective address is in bytes, so the block offset length is ⌈ log 2 ⁡ ( b ) ⌉ {\displaystyle \lceil \log _{2}(b)\rceil } bits, where b is the number of bytes per data block. The tag contains the most significant bits of the address, which are checked against all rows in

2967-435: The execution of subsequent instructions; the processor can continue until the queue is full. For a detailed introduction to the types of misses, see cache performance measurement and metric . Most general purpose CPUs implement some form of virtual memory . To summarize, either each program running on the machine sees its own simplified address space , which contains code and data for that program only, or all programs run in

3036-425: The following structure: The data block (cache line) contains the actual data fetched from the main memory. The tag contains (part of) the address of the actual data fetched from the main memory. The flag bits are discussed below . The "size" of the cache is the amount of main memory data it can hold. This size can be calculated as the number of bytes stored in each data block times the number of blocks stored in

3105-408: The in-memory page table. Both machines predated the first machine with a cache for main memory, the IBM System/360 Model 85 , so the first hardware cache used in a computer system was not a data or instruction cache, but rather a TLB. Caches can be divided into four types, based on whether the index or tag correspond to physical or virtual addresses: The speed of this recurrence (the load latency )

3174-443: The instruction is fetched from main memory. Cache read misses from a data cache usually cause a smaller delay, because instructions not dependent on the cache read can be issued and continue execution until the data is returned from main memory, and the dependent instructions can resume execution. Cache write misses to a data cache generally cause the shortest delay, because the write can be queued and there are few limitations on

3243-400: The instruction that is waiting for the cache miss data. Another technology, used by many processors, is simultaneous multithreading (SMT), which allows an alternate thread to use the CPU core while the first thread waits for required CPU resources to become available. The placement policy decides where in the cache a copy of a particular entry of main memory will go. If the placement policy

3312-472: The largest part of them by chip area, but SRAM is not always used for all levels (of I- or D-cache), or even any level, sometimes some latter or all levels are implemented with eDRAM . Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the translation lookaside buffer (TLB) which is part of the memory management unit (MMU) which most CPUs have. When trying to read from or write to

3381-519: The level-1 data cache in an AMD Athlon is two-way set associative, which means that any particular location in main memory can be cached in either of two locations in the level-1 data cache. Choosing the right value of associativity involves a trade-off . If there are ten places to which the placement policy could have mapped a memory location, then to check if that location is in the cache, ten cache entries must be searched. Checking more places takes more power and chip area, and potentially more time. On

3450-434: The local cache are now stale and should be marked invalid. A data cache typically requires two flag bits per cache line – a valid bit and a dirty bit . Having a dirty bit set indicates that the associated cache line has been changed since it was read from main memory ("dirty"), meaning that the processor has written data to that line and the new value has not propagated all the way to main memory. A cache miss

3519-399: The main memory can be cached in either of two locations in the cache, one logical question is: which one of the two? The simplest and most commonly used scheme, shown in the right-hand diagram above, is to use the least significant bits of the memory location's index as the index for the cache memory, and to have two entries for each index. One benefit of this scheme is that the tags stored in

SECTION 50

#1732854704775

3588-627: The major location in a cache block. Multicolumn cache remains a high hit ratio due to its high associativity, and has a comparable low latency to a direct-mapped cache due to its high percentage of hits in major locations. The concepts of major locations and selected locations in multicolumn cache have been used in several cache designs in ARM Cortex R chip, Intel's way-predicting cache memory, IBM's reconfigurable multi-way associative cache memory and Oracle's dynamic cache replacement way selection based on address tab bits. Cache row entries usually have

3657-419: The new memory location. There are intermediate policies as well. The cache may be write-through, but the writes may be held in a store data queue temporarily, usually so multiple stores can be processed together (which can reduce bus turnarounds and improve bus utilization). Cached data from the main memory may be changed by other entities (e.g., peripherals using direct memory access (DMA) or another core in

3726-404: The newly indexed cache block is a most recently used (MRU) block, it is placed in the major location in multicolumn cache with a consideration of temporal locality. Since multicolumn cache is designed for a cache with a high associativity, the number of ways in each set is high; thus, it is easy find a selected location in the set. A selected location index by an additional hardware is maintained for

3795-496: The original Athlon 64, especially for multi-threaded software. Having two cores, the Athlon 64 X2 has an increased number of transistors . The 1 MB L2 cache 90 nm Athlon 64 X2 processor is 219 mm in size with 243 million transistors whereas its 1 MB L2 cache 90 nm Athlon 64 counterpart is 103.1 mm and has 164 million transistors. The 65 nm Athlon 64 X2 with only 512 KB L2 per Core reduced this to 118 mm with 221 million transistors compared to

3864-540: The other hand, caches with more associativity suffer fewer misses (see conflict misses ), so that the CPU wastes less time reading from the slow main memory. The general guideline is that doubling the associativity, from direct mapped to two-way, or from two-way to four-way, has about the same effect on raising the hit rate as doubling the cache size. However, increasing associativity more than four does not improve hit rate as much, and are generally done for other reasons (see virtual aliasing ). Some CPUs can dynamically reduce

3933-465: The pattern broke down, to allow for larger caches without being forced into the doubling-in-size paradigm, with e.g. Intel Core 2 Duo with 3 MiB L2 cache in April 2008. This happened much later for L1 caches, as their size is generally still a small number of KiB. The IBM zEC12 from 2012 is an exception however, to gain unusually large 96 KiB L1 data cache for its time, and e.g. the IBM z13 having

4002-422: The possible ways simultaneously, using something like a content-addressable memory . A pseudo-associative cache tests each possible way one at a time. A hash-rehash cache and a column-associative cache are examples of a pseudo-associative cache. In the common case of finding a hit in the first way tested, a pseudo-associative cache is as fast as a direct-mapped cache, but it has a much lower conflict miss rate than

4071-414: The processing power of a second core. Programs often written with multiple threads and able to use two cores include many music and video encoding applications, and especially professional rendering programs. High TLP applications currently correspond to server and workstation situations more than the typical desktop. These applications can reach almost twice the performance of a single-core Athlon 64 of

4140-409: The processor finds that the memory location is in the cache, a cache hit has occurred. However, if the processor does not find the memory location in the cache, a cache miss has occurred. In the case of a cache hit, the processor immediately reads or writes the data in the cache line. For a cache miss, the cache allocates a new entry and copies data from main memory, then the request is fulfilled from

4209-405: The same entry, they may continually knock each other out. Although simpler, a direct-mapped cache needs to be much larger than an associative one to give comparable performance, and it is more unpredictable. Let x be block number in cache, y be block number of memory, and n be number of blocks in cache, then mapping is done with the help of the equation x = y mod n . If each location in

SECTION 60

#1732854704775

4278-456: The same month as Intel's first dual-core processor, the Pentium D . In June 2007, AMD released low-voltage variants of their low-end 65 nm Athlon 64 X2 , named " Athlon X2 ". The Athlon X2 processors feature reduced thermal design power (TDP) of 45 Watt (W). The name was also used for K10 based budget CPUs with two cores deactivated. The primary benefit of dual-core processors (like

4347-404: The same specifications. Multitasking also runs a sizable number of threads. Intense multitasking processes have sped up by considerably more than twice. This is mostly due to the high overhead caused by constantly switching threads, and could potentially be improved by adjustments to operating system scheduling code. In the consumer segment of the market, the X2 improves on the performance of

4416-463: The same time. The ability of processors to execute multiple threads simultaneously is called thread-level parallelism (TLP). By placing two cores on the same die, the X2 effectively doubles the TLP over a single-core Athlon 64 of the same speed. The need for TLP processing ability depends on the situation to a great degree, and some situations benefit from it far more than others. Some programs are currently written for only one thread, and thus cannot use

4485-418: The speed gap between the memory performance and the processor performance is increasing exponentially. The cache was introduced to reduce this speed gap. Thus knowing how well the cache is able to bridge the gap in the speed of processor and memory becomes important, especially in high-performance systems. The cache hit rate and the cache miss rate play an important role in determining this performance. To improve

4554-507: The tag field. An instruction cache requires only one flag bit per cache row entry: a valid bit. The valid bit indicates whether or not a cache block has been loaded with valid data. On power-up, the hardware sets all the valid bits in all the caches to "invalid". Some systems also set a valid bit to "invalid" at other times, such as when multi-master bus snooping hardware in the cache of one processor hears an address broadcast from some other processor, and realizes that certain data blocks in

4623-440: The typical desktop. These applications can reach almost twice the performance of a single-core Athlon 64 of the same specifications. Multitasking also runs a sizable number of threads. Intense multitasking processes have sped up by considerably more than twice. This is mostly due to the high overhead caused by constantly switching threads, and could potentially be improved by adjustments to operating system scheduling code. In

4692-573: Was omitted from the name of the Brisbane 'BE' series; the 64-bit marketing campaign initiated by AMD became insignificant once essentially all consumer CPUs became 64-bit processors. Athlon X2 The Athlon 64 X2 is the first native dual-core desktop central processing unit (CPU) designed by Advanced Micro Devices (AMD). It was designed from scratch as native dual-core by using an already multi-CPU enabled Athlon 64 , joining it with another functional core on one die , and connecting both via

4761-399: Was omitted from the name of the Brisbane 'BE' series; the 64-bit marketing campaign initiated by AMD became insignificant once essentially all consumer CPUs became 64-bit processors. CPU cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory . A cache is

#774225