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53-879: The first Alpha Micro computer was the S-100 AM-100, based upon the WD16 microprocessor chipset from Western Digital . As of 1982, AM-100/L and the AM-1000 were based on the Motorola 68000 and succeeding processors, though Alpha Micro swapped several addressing lines to create byte-ordering compatibility with their earlier processor. Early peripherals included standard computer terminals (such models as Soroc, Hazeltine 1500 , and Wyse WY50), Fortran punch card readers , 300 baud rate acoustic coupler modems (later upgraded to 1,200 baud modems), and 10 MB CDC Hawk hard drives with removable disk packs . The company's primary claim to fame

106-458: A PRTN R5 . PRTN doubles the number on the top of stack and adds it to SP, deleting the parameters. PRTN then continues by returning to caller with the equivalent of an RTN R5 , loading R5 into PC and popping R5. These instructions have a 13 bit opcode and a three bit register argument. These instructions are used to implement operating system (supervisor) calls. All have a six bit register argument. SVCB and SVCC are designed so an argument to

159-470: A vectored interrupt is received, PS and PC are pushed. During interrupt acknowledge, the WD16 accepts a four-bit interrupt number provided by the interrupting device. The interrupt vector table address is fetched from 0028 and the interrupt number is added to it, pointing to one of 16 words in the table. A word offset is fetched from the table and added to its own table address. The result is loaded into PC causing

212-474: A (relatively fast) 8-bit processor that can be micro-programmed to emulate a 16-bit CPU. All byte operations execute in one clock period; word operations and branches take two clocks. Up to four MICROMs are supported, but usually two or three could hold the needed microprogram for a processor. The register file consists of 26 8-bit registers. Ten may be addressed directly by the microinstruction (Rx), four may be addressed either directly or indirectly (Rx/Gx), and

265-494: A commodity item. The Alpha Microsystems package often included software that allow traditional multi-user systems, like AMOS and others such as Sun , DEC , HP and IBM mainframes to interface with the Microsoft Windows graphical user interface and supported peripherals. This software functioned similar to Citrix or the X Window System . The Alpha Micro computer never achieved mainstream name recognition, though it

318-488: A jump to the interrupt service routine . What simultaneous interrupts are taken is determined by a 16-bit interrupt priority mask that is mostly implemented with external hardware. The WD16 stores the current priority mask at 002E while transmitting the mask directly to hardware. The mask is manipulated with the MSKO , SAVS , and RSTS instructions. If more than 16 vectored interrupts are required, they can be initiated through

371-479: A stack of words. Autoincrement and autodecrement operations on SP are always by a stride of 2. Most of the WD16 instructions operate on bytes and words. Bytes are specified by a register number—identifying the register's low-order byte—or by a memory location. Words are specified by a register number or by the memory location of the low-order byte, which must be an even number. All opcodes and addresses are expressed in hexadecimal . The high-order four bits specify

424-506: A tokenized executable file. Later versions translate the tokenized executable into x86 code for performance. Other programming languages included AlphaFortran , AlphaLisp and AlphaPascal . In the past, Alpha Micro bundled their operating system and tools such as BASIC and their ISAM implementation as part of the hardware sale, also providing patches and OS upgrades for free or at minimal cost. Gradually, Alpha Micro has transitioned to charging for their software as hardware becomes more of

477-518: A total instruction time of 2.55 microseconds. Any case where addressed memory was not in the cache adds 1.02 microseconds. The register-to-register ADD R m ,R n could execute from the cache in 0.3 microseconds. A single-precision floating add instruction executed by the FP11-C co-processor could range from 0.9 to 2.5 microseconds plus time to fetch the operands which could range up to 4.2 microseconds. The WD16 block transfer instructions approximately double

530-466: Is 3.3 MHz. Its interface to memory is via a 16-bit multiplexed data/address bus. The WD16 is best known for its use in Alpha Microsystems ' AM-100 and AM-100/T processor boards. A prototype was demonstrated in 1977. As of 1981 there were at least 5,000 Alpha Micro computers based on the WD16. As late as 1982, WD16-based Alpha Micros were still being characterized as "supermicros." The WD16

583-630: Is a 16-bit microprocessor introduced by Western Digital in October 1976. It is based on the MCP-1600 chipset, a general-purpose design that was also used to implement the DEC LSI-11 low-end minicomputer and the Pascal MicroEngine processor. The three systems differed primarily in their microcode , giving each system a unique instruction set architecture (ISA). The WD16 implements an extension of

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636-425: Is a 16-bit value taken from a second word of the instruction. In double-operand instructions, both operands can use these modes. Such instructions are three words long. Autoincrement and autodecrement operations on a register are by 1 in byte instructions, by 2 in word instructions, and by 2 whenever a deferred mode is used, since the quantity the register addresses is a (word) pointer. When R7 (the program counter)

689-399: Is another conditional branch instruction. The specified register is decremented by 1 and if the result is not zero, a reverse branch is taken based on the 6-bit word offset. JSR calls a subroutine. A group of six bits specifies the addressing mode. The JSR instruction can save any register on the stack. Programs that do not need this feature specify PC as the register ( JSR PC, address ) and

742-442: Is as follows: In the following sections, each item includes an example of how the operand would be written in assembly language. Rn means one of the eight registers, written R0 through R7. The following eight modes can be applied to any general register. Their effects when applied to R6 (the stack pointer, SP) and R7 (the program counter, PC) are set out separately in the following sections. In index and index deferred modes, X

795-486: Is contained in R0 as a unsigned integer. The count ranges from 1–65536. These instructions are fully interruptible. The high-order byte of the instruction specifies the operation. The low-order byte is a signed word offset relative to the current location of the program counter. This allows for forward and reverse branches in code. Maximum branch range is +128, -127 words from the branch op code. In most branch instructions, whether

848-431: Is more typical for referring to program variables and jump destinations. A program that uses relative mode (and relative deferred mode) exclusively for internal references is position-independent ; it contains no assumptions about its own location, so it can be loaded into an arbitrary memory location, or even moved, with no need for its addresses to be adjusted to reflect its location. In computing such addresses relative to

901-521: Is significantly slower. A single-and-a-half precision (48 bit) floating add instruction typically ranges from 54 to 126 microseconds. The WD16's precision is a compromise between traditional single and double precision floats. For contrast, the fastest PDP-11 computer at the time was the PDP-11/70. An instruction of the form ADD  x (R m ), y (R n ) has a fetch/execute time of 1.35 microseconds plus source and destination times of 0.6 microseconds each, for

954-412: Is specified, four of the addressing modes naturally yield useful effects: There are only two common uses of absolute mode, whose syntax combines immediate and deferred mode. The first is accessing the reserved processor locations at 0000-003F. The other is to specify input/output registers in port space, as the registers for each device have specific memory addresses. Relative mode has a simpler syntax and

1007-417: Is the program counter (PC). Although any register can be used as a stack pointer, R6 is the stack pointer (SP) used for hardware interrupts and traps. R0 is the count for the block transfer instructions. Most instructions allocate six bits to specify each operand. Three bits select one of eight addressing modes and three bits select a general register. The encoding of the six bit operand addressing mode

1060-533: Is true zero (all zeros). 3. A 40 bit mantissa with the MSB implied. The WD16's 16-bit addresses can directly access 64  KB of memory. The WD16 does not offer any inherent memory management or protection. In the AM-100 application, the last 256 memory locations are mapped to port space. As most AM-100 computers were used as multi-user computers, the memory would usually be expanded past 64K with bank switching . Although

1113-421: Is used as a hardware stack for traps and interrupts. A convention enforced by the set of addressing modes the WD16 provides is that a stack grows downward—toward lower addresses—as items are pushed onto it. When a mode is applied to SP, or to any register the programmer elects to use as a software stack, the addressing modes have the following effects: Although software stacks can contain bytes, SP always points to

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1166-453: Is used for only two things: power fail and line clock. (A line clock is typically a 50 or 60 Hz input used for time slicing and time keeping .) When a NVI is received, PS and PC are pushed. Power fail status is checked. If it is a power fail, the WD16 will jump to the address stored at 0014. If not a power fail, then a line clock tick is assumed and the WD16 will jump to the address stored at 002A. Sixteen interrupt vectors are supported. When

1219-481: The HALT instruction is executed, it may be cleared by the halt line, again, depending on jumpers. Memory locations between 0000 and 003F have fixed functions defined by the processor. All addresses below are word addresses. WD16 processor speed varies by clock speed, memory configuration, op code, and addressing modes. Instruction timing has up to three components, fetch/execute of the instruction itself and access time for

1272-622: The Alpha Microsystems AM-100, and the DEC LSI-11 microcomputer, a cost-reduced and compact implementation of the DEC PDP-11 . There are three types of chips in the chip-set: The chips use a 3.3 MHz four phase clock and three power supply voltages (+5V, +12V, and -5V), as required by the N-channel silicon gate process then available at Western Digital. Internally the MCP-1600 is

1325-604: The PDP-11 instruction set architecture but is not machine code compatible with the PDP-11. The instruction set and microcoding were created by Dick Wilcox and Rich Notari. The WD16 is an example of orthogonal CISC architecture . Most two-operand instructions can operate memory-to-memory with any addressing mode and some instructions can result in up to ten memory accesses. The WD16 is implemented in five 40-pin DIP packages. Maximum clock speed

1378-538: The 1611, and later became a Senior VP at Silicon Storage Technology . Bill Pohlman was the design engineering manager and he later was Project Manager for the Intel 8086 processor. Microcode could be developed using a DEC LSI-11 computer with the KUV11-AA Writable Control Store (WCS) option. This option allowed programming of the internal 8-bit micromachine to create application-specific extensions to

1431-507: The AM-100 could be configured for up to 22 users and 512 Kilobytes of RAM, a typical memory configuration for a 9-user AM-100 might be in the range of 352 Kilobytes. In 1981 an optional AM-700 memory management unit was offered for the AM-100/T which allowed memory segmentation in 256 byte increments. The CPU contains eight general-purpose 16-bit registers , R0 to R7. The registers can be used for any purpose with these exceptions: Register R7

1484-500: The NVI and dispatched with the IAK instruction. Halt is a non-maskable interrupt that can be used for a programmer's switch or other uses depending on how its jumpers are configured. Although halt can alter the execution address and is not masked by interrupt enable, it cannot be used a typical non-maskable interrupt because PC is not pushed. Depending on jumpers, the halt line may not even halt. If

1537-471: The PC and the top element of the stack, and so permit the two routines to swap control and resume operation where each was terminated by the previous swap. PRTN deletes a number of parameters from the stack and returns. PRTN is the WD16's answer to the PDP-11's convoluted MARK instruction. Unlike MARK, PRTN executes in program space and can use any register as a linkage register. For this explanation, R5 will be used as

1590-431: The address of the operand, the equivalent of addressing mode (Rn). If field I = 1, designated register contains the address of the address of the operand, the equivalent of addressing mode @0(Rn). Opcodes F500 to FFFF were mapped to a fourth microm to implement eleven more floating point instructions. There is no evidence that this fourth microm was ever produced. When a standard WD16 processor executes opcodes F500 to FFFF,

1643-423: The branch is taken is based on the state of the condition codes. A branch instruction is typically preceded by a two-operand CMP (compare) or BIT (bit test) or a one-operand TST (test) instruction. Arithmetic and logic instructions also set the condition codes. In contrast to Intel processors in the x86 architecture , MOV instructions set them too, so a branch instruction could be used to branch depending on whether

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1696-447: The caller's code resumes. Such a routine would specify RTN R4 to return to its caller. The JSR PC,@(SP)+ form can be used to implement coroutines . Initially, the entry address of the coroutine is placed on the stack and from that point the JSR PC,@(SP)+ instruction is used for both the call and the return statements. The result of this JSR instruction is to exchange the contents of

1749-431: The current location, the processor performs relocation on the fly. Immediate and absolute modes are merely autoincrement and autoincrement deferred mode, respectively, applied to PC. When the auxiliary word is in the instruction, the PC for the next instruction is automatically incremented past the auxiliary word. As PC always points to words, the autoincrement operation is always by a stride of 2. R6, also written SP,

1802-530: The decode of a macroinstruction. The PTA was designed specifically to eliminate most of the overhead of macroinstruction translation. Essentially a macroinstruction opcode is quickly translated into an address that is loaded onto the Location Counter, creating a jump to the appropriate microcode to handle the macroinstruction. John Wallace was the Project Manager and designed the 1621, Mike Briner designed

1855-399: The foundation for AMOS 8.x, which runs natively on x86, but includes a 68K emulator to run older software in a method similar to Apple Inc. 's Mac 68k emulator for PowerPC . For application development, AMOS used a proprietary BASIC-like language called AlphaBASIC (though several other languages, including Assembler, FORTRAN, Pascal, and COBOL, were available). Older versions interpreted

1908-592: The instruction set. The WCS is a quad Q-Bus board with a ribbon cable connecting to an open MCP-1600 microcode ROM socket. In March 1976, it was announced that National Semiconductor would second-source the MCP-1600. It is unclear whether any were produced by National. A clone of the CP1611 and CP1621 was manufactured in the Soviet Union under the designation KR581IK1 and KR581IK2 ( Russian : КР581ИК1 and КР581ИК2 ). The Soviet 581 series included other members of

1961-459: The linkage. First, the caller pushes R5 on the stack. Next, any number of word arguments may be placed on the stack. The caller then puts the number of argument words + 1 into R5. The caller executes a JSR R5,address instruction which pushes the number of argument words + 1 onto the stack, places the return address in R5, and jumps to the subroutine. After executing its code, the subroutine terminates with

2014-479: The lower word being stored in the lower-numbered register. 32 bit values are used by MUL, DIV and some rotate and arithmetic shift instructions. Floating point values are 48 bits long and can only be stored in memory. This format is half-way between single and double precision floating point formats. They are stored an unusual middle-endian format sometimes referred to as "PDP-endian." Floating point values are always aligned to even addresses. The first word contains

2067-455: The operand addressing mode and three bits specify a register or register pair. Where a register pair is used (written below as "Reg+1:Reg") Reg contains the low-order portion of the operand. The next higher numbered register contains the high-order portion of the operand (or the remainder). The high-order ten bits specify the operation to be performed, with bit 15 generally selecting byte versus word addressing. A single group of six bits specifies

2120-500: The operand as defined above. The high-order seven bits and bits 5 and 4 specify the operation to be performed. A single group of three bits specifies the register. A four bit count field contains a small immediate or a count. In all cases one is added to this field making the range 1 through 16. The high-order eight bits specify the operation to be performed. Two groups of four bits specify the source and destination addressing mode and register. If field I = 0, designated register contains

2173-487: The operating system can use most of the addressing modes supported by the native instruction set. The four condition codes in the processor status word (PSW) are WD16 has three types of interrupts: non-vectored, vectored, and halt. Non-vectored and vectored interrupts are enabled and disabled by the IEN and IDS instructions. Halt cannot be disabled. A non-vectored interrupt (NVI) has priority over vectored interrupts. The NVI

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2226-419: The operation to be performed. Two groups of six bits specify the source operand addressing mode and the destination operand addressing mode, as defined above. This group of instructions takes up 75% of available opcodes. Some two-operand instructions utilize an addressing mode for one operand and a register for the second operand: The high-order seven bits specify the operation to be performed, six bits specify

2279-434: The remaining 12 may be addressed only indirectly (Gx). Indirect addressing is via a 3-bit G register which is usually loaded with the register field of the PDP-11 instruction. The most significant feature of the MCP-1600 is its Programmable Translation Array (PTA). The PTA serves to generate new microinstruction fetch addresses as a function of several parameters. These parameters are those which are normally considered during

2332-455: The reserved opcode trap is taken, loading PC from 001A. The high-order ten bits specify the operation to be performed. Two groups of three bits specify the source and destination registers. In all cases the source register contains the address of the first word or byte of memory to be moved, and the destination register contains the address of the first word or byte of memory to receive the data being moved. The number of words or bytes being moved

2385-451: The same, unsuccessfully tried to sue Alpha Micro over the similarities in 1984. As Motorola stopped developing their 68000 product, Alpha Micro started to move to the x86 CPU family, used in common PCs. This was initially done with the Falcon cards, allowing standard DOS and later Windows-based PCs to run AMOS applications on the 68000-series CPU on the Falcon card. The work done on AMPC became

2438-431: The sign, exponent, and high byte of the mantissa. The next higher address contains the middle two bytes of the mantissa, and the next higher address contains the lowest two bytes of the mantissa. The complete format is as follows: 1. A 1 bit sign for the entire number which is zero for positive. 2. An 8-bit base-two exponent in excess-128 notation with a range of +127, -128. The only legal number with an exponent of -128

2491-430: The source and the destination. The last two components depend on the addressing mode. For example, at 3.3 MHz, an instruction of the form ADD  x (R m ), y (R n ) has a fetch/execute time of 3.3 microseconds plus source time of 2.7 microseconds and destination time of 3.0 microseconds, for a total instruction time of 9.0 microseconds. The register-to-register ADD R m ,R n executes in 3.3 microseconds. Floating point

2544-418: The speed of moves and block I/O. A word moved with MOV (R1)+,(R2)+, SOB R0,loop instructions takes 9.6 microseconds per iteration. The MBWU R1,R2 equivalent takes 4.8 microseconds per iteration. MCP-1600 The MCP-1600 is a multi-chip 16-bit microprocessor introduced by Western Digital in 1975 and produced through the early 1980s. Used in the Pascal MicroEngine , the WD16 processor in

2597-460: The subroutine returns using RTN PC . If a routine were called with, for example JSR R4, address , then the old value of R4 would be saved on the top of the stack and the return address (just after JSR) would be in R4. This lets the routine gain access to values coded in-line by specifying (R4)+ or to in-line pointers by specifying @(R4)+. The autoincrementation moves past these data, to the point at which

2650-491: The value moved was zero or negative. The limited range of the branch instructions meant that as code grows, the target addresses of some branches may become unreachable. The programmer would change the one-word Bcc to the two-word JMP instruction. As JMP has no conditional forms, the programmer would change the Bcc to its opposite sense to branch around the JMP. SOB (Subtract One and Branch)

2703-455: Was popular in certain vertical markets, particularly medical, law, and dental offices. There were two organizations which produced periodic newsletters and held annual meetings; AMUS (Alpha Micro Users Society), and IAMDA (International Alpha Micro Dealer's Association). It was typically at these annual meetings that the latest hardware and software products were announced by Alpha Microsystems and third party developers. WD16 The WD16

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2756-518: Was selling inexpensive minicomputers that provided multi-user power using a proprietary operating system called AMOS ( Alpha Micro Operating System ). The operating system on the 68000 machines was called AMOS/L. The operating system had major similarities to the operating system of the DEC DECsystem-10 . This may not be coincidental; legend has it that the founders based their operating system on "borrowed" source code from DEC, and DEC, perceiving

2809-502: Was superseded by the Motorola 68000 in June 1982. The smallest unit of addressable and writable memory is the 8-bit byte . Bytes can also be held in the lower half of registers R0 through R5. 16-bit words are stored little-endian with least significant bytes at the lower address. Words are always aligned to even memory addresses. Words can be held in registers R0 through R7. 32-bit double words can only be stored in register pairs with

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