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54-622: Like modern analog VGA connectors, the DVI and DisplayPort connectors include pins for DDC, but DisplayPort only supports DDC within its optional Dual-Mode DP ( DP++ ) feature in DVI/HDMI mode. The standard was created by the Video Electronics Standards Association (VESA). The DDC suite of standards aims to provide Plug and Play and DPMS power management experiences for computer displays. DDC1 and DDC2B/Ab/B+/Bi protocols are

108-474: A gross bit rate that is 10 times the frequency of the TMDS clock. In each TMDS clock period there is a 10-bit symbol per TMDS data pair representing 8-bits of pixel color. In single link mode each set of three 10-bit symbols represents one 24-bit pixel, while in dual link mode each set of six 10-bit symbols either represents two 24-bit pixels or one pixel of up to 48-bit color depth . The specification document allows

162-593: A video display controller , to a display device , such as a computer monitor . It was developed with the intention of creating an industry standard for the transfer of uncompressed digital video content. DVI devices manufactured as DVI-I have support for analog connections, and are compatible with the analog VGA interface by including VGA pins, while DVI-D devices are digital-only. This compatibility, along with other advantages, led to its widespread acceptance over competing digital display standards Plug and Display (P&D) and Digital Flat Panel (DFP). Although DVI

216-597: A DDC-capable monitor was connected. The DDC signal can be sent to or from a video graphics array (VGA) monitor with the IC protocol using the master's serial clock and serial data pins. DDC1 is a simple, low-speed, unidirectional serial link protocol. Pin 12, ID1 functions as a data line that continuously transmits the 128-byte EDID block, and the data clock is synchronised with vertical sync , providing typical clock rates of 60 to 100 Hz. Very few display devices implemented this protocol. The most common version, called DDC2B ,

270-464: A DVI-D source because HDMI and DVI-D both define an overlapping minimum set of supported resolutions and frame buffer formats. Some DVI-D sources use non-standard extensions to output HDMI signals including audio (e.g. ATI 3000-series and NVIDIA GTX 200-series ). Some multimedia displays use a DVI to HDMI adapter to input the HDMI signal with audio. Exact capabilities vary by video card specifications. In

324-448: A large frequency range. One benefit of DVI over other interfaces is that it is relatively straightforward to transform the signal from the digital domain into the analog domain using a video DAC , as both clock and synchronization signals are transmitted. Fixed frequency interfaces, like DisplayPort , need to reconstruct the clock from the transmitted data. The DVI specification includes signaling for reducing power consumption. Similar to

378-449: A male DVI-I to a female DVI-D. It is possible, however, to join a male DVI-D connector with a female DVI-I connector. DVI is the only widespread video standard that includes analog and digital transmission in the same connector. Competing standards are exclusively digital: these include a system using low-voltage differential signaling ( LVDS ), known by its proprietary names FPD-Link (flat-panel display) and FLATLINK; and its successors,

432-533: A mouse or keyboard with little to no additional effort. Such devices and monitors were briefly available in the mid-1990s, but they disappeared with the introduction of USB . DDC2B+ and DDC2Bi are scaled-down versions of DDC2Ab which only support monitor and graphics card devices but still allow bidirectional communication between them. DDC2 is not exclusive to the VGA interface. Both DVI and HDMI feature dedicated DDC2B wires. DDC/CI ( Command Interface ) standard

486-408: A physical link between a monitor and a video card, which was originally carried on either two or three pins in a 15-pin analog VGA connector . Extended display identification data (EDID) is a companion standard; it defines a compact binary file format describing the monitor's capabilities and supported graphics modes, stored in a read-only memory ( EEPROM ) chip programmed by the manufacturer of

540-659: A preferred mode or native resolution . Each mode is a set of timing values that define the duration and frequency of the horizontal/vertical sync, the positioning of the active display area, the horizontal resolution, vertical resolution, and refresh rate. The maximum length recommended for DVI cables is not included in the specification, since it is dependent on the TMDS clock frequency. In general, cable lengths up to 4.5 metres (15 ft) will work for display resolutions up to 1920 × 1200. Longer cables up to 15 metres (49 ft) in length can be used with display resolutions 1280 × 1024 or lower. For greater distances,

594-418: A receiver can fully differentiate between active and control regions. When DVI was designed, most computer monitors were still of the cathode-ray tube type that require analog video synchronization signals. The timing of the digital synchronization signals matches the equivalent analog ones, so the process of transforming DVI to and from an analog signal does not require extra (high-speed) memory, expensive at

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648-545: A separate standard and introduced the DDC2B+ protocol. DDC version 3 , December 1997, introduced the DDC2Bi protocol and support for VESA Plug and Display and Flat Panel Display Interface on separate device addresses, requiring them to comply with EDID 2.0. The DDC standard has been superseded by E-DDC in 1999. DDC is also used as a communication channel for implementing High-bandwidth Digital Content Protection (HDCP). Prior to

702-485: A single transmitter with a TMDS clock up to 165 MHz that supports resolutions up to 1920 × 1200 at 60 Hz. Dual link DVI adds six pins, at the center of the connector, for a second transmitter increasing the bandwidth and supporting resolutions up to 2560 × 1600 at 60 Hz. A connector with these additional pins is sometimes referred to as DVI-DL (dual link). Dual link should not be confused with dual display (also known as dual head ), which

756-467: A system DMA controller actually does the transfer. Some types of buses allow only one device (typically the CPU , or its proxy) to initiate transactions. Most modern bus architectures, such as PCI , allow multiple devices to bus master because it significantly improves performance for general-purpose operating systems . Some real-time operating systems prohibit peripherals from becoming bus masters, because

810-422: A video source with DVI-I through the use of a passive adapter. Since the analog pins are directly compatible with VGA signaling, passive adapters are simple and cheap to produce, providing a cost-effective solution to support VGA on DVI. The long flat pin on a DVI-I connector is wider than the same pin on a DVI-D connector, so even if the four analog pins were manually removed, it still wouldn't be possible to connect

864-483: Is a VESA standard which can easily be calculated with the Linux gtf utility. Coordinated Video Timings -Reduced Blanking (CVT-RB) is a VESA standard which offers reduced horizontal and vertical blanking for non-CRT based displays. One of the purposes of DVI stream encoding is to provide a DC-balanced output that reduces decoding errors. This goal is achieved by using 10-bit symbols for 8-bit or less characters and using

918-427: Is a configuration consisting of a single computer connected to two monitors, sometimes using a DMS-59 connector for two single link DVI connections. In addition to digital, some DVI connectors also have pins that pass an analog signal, which can be used to connect an analog monitor. The analog pins are the four that surround the flat blade on a DVI-I or DVI-A connector. A VGA monitor, for example, can be connected to

972-417: Is a newer digital audio/video interface developed and promoted by the consumer electronics industry . DVI and HDMI have the same electrical specifications for their TMDS and VESA/DDC twisted pairs. However HDMI and DVI differ in several key ways. To promote interoperability between DVI-D and HDMI devices, HDMI source components and displays support DVI-D signaling. For example, an HDMI display can be driven by

1026-552: Is based on I²C , a serial bus . Pin 12, ID1, of the VGA connector is used as the data pin of the I²C bus, and the formerly-unused pin 15 is the I²C clock. Pin 9, previously used as a mechanical key, supplies +5V DC power (up to 50mA) to power the EEPROM. With this, the host can read the EDID even if the monitor is powered off. Though I²C is fully bidirectional and supports multiple bus-masters , DDC2B

1080-495: Is not a requirement. In single link mode, the maximum TMDS clock frequency is 165 MHz, which supports a maximum resolution of 2.75  megapixels (including blanking interval ) at 60 Hz refresh. For practical purposes, this allows a maximum 16:10 screen resolution of 1920 × 1200 at 60 Hz. To support higher-resolution display devices, the DVI specification contains a provision for dual link . Dual link DVI doubles

1134-465: Is predominantly associated with computers, it is sometimes used in other consumer electronics such as television sets and DVD players . An earlier attempt to promulgate an updated standard to the analog VGA connector was made by the Video Electronics Standards Association (VESA) in 1994 and 1995, with the Enhanced Video Connector (EVC), which was intended to consolidate cables between

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1188-417: Is to keep compatibility with the previous VGA cables and connectors . VGA pins for HSync, Vsync and three video channels are available in both DVI-I or DVI-A (but not DVI-D) connectors and are electrically compatible, while pins for DDC (clock and data) and 5 V power and ground are kept in all DVI connectors. Thus, a passive adapter can interface between DVI-I or DVI-A (but not DVI-D) and VGA connectors. HDMI

1242-498: Is unidirectional and allows only one bus master —the graphics adapter. The monitor acts as a slave device at the 7-bit I²C address 50h, and provides 128-256 bytes of read-only EDID. Because this access is always a read, the first I²C octet will always be A1h. DDC2Ab is an implementation of the I²C-based 100-kbit/s ACCESS.bus interface, which made it possible for monitor manufacturers to support external ACCESS.bus peripherals such as

1296-590: The LVDS Display Interface (LDI) and OpenLDI . Some DVD players , HDTV sets, and video projectors have DVI connectors that transmit an encrypted signal for copy protection using the High-bandwidth Digital Content Protection (HDCP) protocol. Computers can be connected to HDTV sets over DVI, but the graphics card must support HDCP to play content protected by digital rights management (DRM). Generalized Timing Formula (GTF)

1350-498: The 4 ID pins while manipulating the HSync and VSync signals in order to extract 16 bits (4 ID pin values for each of the 4 combinations of HSync and VSync states) of monitor identification. DDC changed the purpose of the ID pins to incorporate a serial link interface . However, during the transition, the change was not backwards-compatible and video cards using the old scheme could have problems if

1404-492: The DDC, the VGA standard had reserved four pins in the analog VGA connector , known as ID0, ID1, ID2 and ID3 (pins 11, 12, 4 and 15) for identification of monitor type. These ID pins, attached to resistors to pull one or more of them to ground (GND), allowed for the definition of the monitor type, with all open (n/c, not connected) meaning "no monitor". In the most commonly documented scheme,

1458-549: The DVI connector includes pins for the display data channel (DDC), which allows the graphics adapter to read the monitor's extended display identification data (EDID). When a source and display using the DDC2 revision are connected, the source first queries the display's capabilities by reading the monitor EDID block over an I²C link. The EDID block contains the display's identification, color characteristics (such as gamma value), and table of supported video modes. The table can designate

1512-423: The EDID memory in the monitor, limiting the storage size to 2 bytes = 256 bytes, but allowing the use of cheap 2-Kbit EEPROMs. In E-DDC, a special I²C addressing scheme was introduced, in which multiple 256-byte segments could be selected. To do this, a single 8-bit segment index is passed to the display via the I²C address 30h. (Because this access is always a write, the first I²C octet will always be 60h.) Data from

1566-544: The EVC connector was reused by VESA, which released the Plug & Display (P&D) standard in 1997. P&D offered single-link TMDS digital video with, as an option, analog video output and data (USB and FireWire), using a 35-pin MicroCross connector similar to EVC; the analog audio and video input lines from EVC were repurposed to carry digital video for P&D. Because P&D

1620-499: The ID3 pin was unused and only the 3 remaining pins were defined. The ID0 was pulled to GND by color monitors, while the monochrome monitors pulled ID1 to GND. Finally, the ID2 pulled to GND signaled a monitor capable of 1024×768 resolution, such as IBM 8514 . In this scheme, the input states of the ID pins would encode the monitor type as follows: More elaborate schemes also existed that used all of

1674-571: The analog VESA display power management signaling (DPMS) standard, a connected device can turn a monitor off when the connected device is powered down, or programmatically if the display controller of the device supports it. Devices with this capability can also attain Energy Star certification. The analog section of the DVI specification document is brief and points to other specifications like VESA VSIS for electrical characteristics and GTFS for timing information. The motivation for including analog

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1728-453: The best connectivity options moving forward. In our opinion, DisplayPort 1.2 is the future interface for PC monitors, along with HDMI 1.4a for TV connectivity". Bus mastering In computing , bus mastering is a feature supported by many bus architectures that enables a device connected to the bus to initiate direct memory access (DMA) transactions. It is also referred to as first-party DMA , in contrast with third-party DMA where

1782-476: The computer and monitor. EVC used a 35-pin Molex MicroCross connector and carried analog video (input and output), analog stereo audio (input and output), and data (via USB and FireWire ). At the same time, with the increasing availability of digital flat-panel displays, the priority shifted to digital video transmission, which would remove the extra analog/digital conversion steps required for VGA and EVC;

1836-511: The data and the clock to not be aligned. However, as the ratio between the TMDS clock and gross bit rate per TMDS pair is fixed at 1:10, the unknown alignment is kept over time. The receiver must recover the bits on the stream using any of the techniques of clock/data recovery to find the correct symbol boundary. The DVI specification allows the TMDS clock to vary between 25 MHz and 165 MHz. This 1:6.6 ratio can make clock recovery difficult, as phase-locked loops , if used, need to work over

1890-689: The display, but the degree of system integration vary. Windows exposes DDC/CI as the Monitor Configuration Win32 API series. Enhanced Display Data Channel ( E-DDC ) is the most recent revision of the DDC standard. Version 1 was introduced in September 1999 and featured the addition of a segment pointer which allowed up to 32 Kbytes of display information storage for use by the Enhanced EDID (E-EDID) standard. Earlier DDC implementations used simple 8-bit data offset when communicating with

1944-465: The extra bits for the DC balancing. Like other ways of transmitting video, there are two different regions: the active region, where pixel data is sent, and the control region, where synchronization signals are sent. The active region is encoded using transition-minimized differential signaling , where the control region is encoded with a fixed 8b/10b encoding . As the two schemes yield different 10-bit symbols,

1998-1031: The first 256-byte segment is performed. The auto-reset mechanism is to provide for backward compatibility to, for example, DDC2B hosts, otherwise they may be stuck at a segment other than 00h in some rare cases. Other important changes were removal of the DDC1 and DDC2Ab protocols, deprecation of separate VESA P&D and FPDI device addresses, and clarifications to the DDC power requirements. E-DDC Version 1.1 , approved March 2004, featured support for HDMI and consumer electronics. E-DDC Version 1.2 , approved December 2007, introduced support for DisplayPort (which has no dedicated DDC2B links and uses its bidirectional auxiliary channel for EDID and MCCS communication) and DisplayID standards. E-DDC Version 1.3 from September 2017 contains corrections for errata and minor clarifications. Some KVM switches (keyboard-video-mouse) and video extenders handle DDC traffic incorrectly, making it necessary to disable monitor plug and play features in

2052-639: The first DVI monitors was Apple's original Cinema Display , which launched in 1999. DVI's digital video transmission format is based on panelLink , a serial format developed by Silicon Image that utilizes a high-speed serial link called transition minimized differential signaling (TMDS). Digital video pixel data is transported using multiple TMDS twisted pairs . At the electrical level, these pairs are highly resistant to electrical noise and other forms of analog distortion . A single link DVI connection has four TMDS pairs. Three data pairs carry their designated 8-bit RGB component (red, green, or blue) of

2106-416: The monitor's color balance. Some tilting DDC/CI monitors support an auto-pivot function, where a rotation sensor in the monitor enables the operating system to keep the display upright as the monitor is moved between its portrait and landscape positions. Most DDC/CI monitors support only a small subset of MCCS commands and some have undocumented commands. Many manufacturers did not pay attention to DDC/CI in

2160-629: The monitor. The format uses a description block containing 128 bytes of data, with optional extension blocks to provide additional information. The most current version is Enhanced EDID (E-EDID) Release A, v2.0 . DisplayID is aim to replace EDID, which supports many features such as HDR and color management . The first version of the DDC standard was adopted in August 1994. It included the EDID 1.0 format and specified DDC1, DDC2B and DDC2Ab physical links. DDC version 2 , introduced in April 1996, split EDID into

2214-553: The number of TMDS data pairs, effectively doubling the video bandwidth, which allows higher resolutions up to 2560 × 1600 at 60 Hz or higher refresh rates for lower resolutions. For backward compatibility with displays using analog VGA signals, some of the contacts in the DVI connector carry the analog VGA signals. To ensure a basic level of interoperability, DVI compliant devices are required to support one baseline display mode , "low pixel format" (640 × 480 at 60 Hz). Like modern analog VGA connectors ,

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2268-477: The operating system, and maybe even physically remove pin 12 (serial data pin) from the analog VGA cables that connect such device to multiple PCs. Microsoft Windows features a standard "Plug and Play Monitor" driver which uses the display's EDID information to construct a list of supported monitor modes. The Display Resolution control panel applet can be used to disable this driver's Plug and Play features and manually select any resolution or refresh rate supported by

2322-460: The past, but now almost all monitors support such general MCCS commands as brightness and contrast management. DDC/CI standard describes a full suite of bidirectional control protocols - DDC2Ab, DDC2Bi and DDC2B+ - in a single standard and provides a means for packaging Monitor Control Command Set commands. DDC/CI version 1.1 was adopted in October 2004. Monitor Control Command Set version 2.0

2376-820: The reverse scenario, a DVI display that lacks optional support for HDCP might be unable to display protected content even though it is otherwise compatible with the HDMI source. Features specific to HDMI such as remote control, audio transport, xvYCC and deep color are not usable in devices that support only DVI signals. HDCP compatibility between source and destination devices is subject to manufacturer specifications for each device. In December 2010, Intel , AMD , and several computer and display manufacturers announced they would stop supporting DVI-I, VGA and LVDS -technologies from 2013/2015, and instead speed up adoption of DisplayPort and HDMI. They also stated: "Legacy interfaces such as VGA, DVI and LVDS have not kept pace, and newer standards such as DisplayPort and HDMI clearly provide

2430-438: The scheduler can no longer arbitrate for the bus and hence cannot provide deterministic latency. While bus mastering theoretically allows one peripheral device to directly communicate with another, in practice almost all peripherals master the bus exclusively to perform DMA to main memory . If multiple devices are able to master the bus, there needs to be a bus arbitration scheme to prevent multiple devices attempting to drive

2484-445: The selected segment is then immediately read via the regular DDC2 address using a repeated I²C 'START' signal. However, VESA specification defines the segment index value range as 00h to 7Fh, so this only allows addressing 128 segments × 256 bytes = 32  KiB . The segment index register is volatile, defaulting to zero and automatically resetting to zero after each NACK or STOP. Therefore, it must be set every time access to data above

2538-403: The single-link P&D and DFP connectors, which led to its successful adoption as an industry standard. Compatibility of DVI with P&D and DFP is accomplished typically through passive adapters that provide appropriate physical interfaces, as all three standards use the same DDC/EDID handshaking protocols and TMDS digital video signals. DVI made its way into products starting in 1999. One of

2592-457: The time. HDCP is an extra layer that transforms the 10-bit symbols before transmitting. Only after correct authorization can the receiver undo the HDCP encryption. Control regions are not encrypted in order to let the receiver know when the active region starts. DVI provide one TMDS clock pair and 3 TMDS data pairs in single link mode or 6 TMDS data pairs in dual link mode. TMDS data pairs operate at

2646-409: The use of a DVI booster—a signal repeater which may use an external power supply—is recommended to help mitigate signal degradation. The DVI connector on a device is given one of three names, depending on which signals it implements: Most DVI connector types—the exception is DVI-A—have pins that pass digital video signals. These come in two varieties: single link and dual link. Single link DVI employs

2700-492: The video card. Many video card manufacturers and third parties provide control applications which can be used to select a custom display mode that does not conform to the EDID information or the monitor .INF file. DVI Digital Visual Interface ( DVI ) is a video display interface developed by the Digital Display Working Group (DDWG). The digital interface is used to connect a video source, such as

2754-561: The video signal for a total of 24 bits per pixel . The fourth pair carries the TMDS clock. The binary data is encoded using 8b/10b encoding . DVI does not use packetization , but rather transmits the pixel data as if it were a rasterized analog video signal. As such, the complete frame is drawn during each vertical refresh period. The full active area of each frame is always transmitted without compression. Video modes typically use horizontal and vertical refresh timings that are compatible with cathode-ray tube (CRT) displays, though this

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2808-542: Was a physically large, expensive connector, a consortium of companies developed the DFP standard (1999), which was focused solely on digital video transmission using a 20-pin micro ribbon connector and omitted the analog video and data capabilities of P&D. DVI instead chose to strip just the data functions from P&D, using a 29-pin MicroCross connector to carry digital and analog video. Critically, DVI allows dual-link TMDS signals, meaning it supports higher resolutions than

2862-449: Was adopted in October 2003. A new MCCS V3 was introduced in July 2006, though did not gain enough industry attention yet. The latest release of V2 standard is version 2.2a, adopted January 2011. Despite its ubiquity in post-2016 displays, DDC/CI is not generally used by the operating system by default for brightness control on external displays. Additional software can be used to send commands to

2916-431: Was introduced in August 1998. It specifies a means for a computer to send commands to the monitor, as well as receive sensor data from the monitor, over a bidirectional link. Specific commands to control monitors are defined in a separate Monitor Control Command Set (MCCS) standard version 1.0, released in September 1998. DDC/CI monitors are sometimes supplied with an external color sensor to allow automatic calibration of

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