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43-578: The T1100 PLUS is a later model of this laptop, released to the market in 1986. Some significant differences to the T1100 are: 16-bit data bus 80C86 CPU, 7.16 MHz or 4.77 MHz operation, 256 KB of conventional RAM (16-bit) extendable to 640 KB, and two internal 720 KB 3.5" diskette drives. The T1100 was named an IEEE Milestone in 2009. Toshiba T1100 PLUS was cloned in the USSR as Electronika MS 1504 in 1991. This computer hardware article

86-474: A 20- bit or 24-bit segment or selector-offset address representation to extend the range of addressable memory locations beyond what was possible using only 16-bit addresses. Programs containing more than 2 bytes (65,536 bytes ) of instructions and data therefore required special instructions to switch between their 64-kilobyte segments , increasing the complexity of programming 16-bit applications. WDC 65816 The W65C816S (also 65C816 or 65816 )

129-709: A similar fashion, later 68000-family members, starting with the Motorola 68020 , had 32-bit ALUs. One may also see references to systems being, or not being, 16-bit based on some other measure. One common one is when the address space is not the same size of bits as the internal registers. Most 8-bit CPUs of the 1970s fall into this category; the MOS 6502 , Intel 8080 , Zilog Z80 and most others had 16-bit address space which provided 64 KB of address space. This also meant address manipulation required two instruction cycles. For this reason, most processors had special 8-bit addressing modes,

172-596: Is a stub . You can help Misplaced Pages by expanding it . 16-bit In computer architecture , 16-bit integers , memory addresses , or other data units are those that are 16 bits (2 octets ) wide. Also, 16-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers , address buses , or data buses of that size. 16-bit microcomputers are microcomputers that use 16-bit microprocessors . A 16-bit register can store 2 different values. The range of integer values that can be stored in 16 bits depends on

215-786: Is a 16-bit microprocessor (MPU) developed and sold by the Western Design Center (WDC). Introduced in 1983, the W65C816S is an enhanced version of the WDC 65C02 8-bit MPU, itself a CMOS enhancement of the venerable MOS Technology 6502 NMOS MPU. The 65C816 is the CPU for the Apple IIGS and, in modified form, the Super Nintendo Entertainment System . The 65 in the part's designation comes from its 65C02 compatibility mode, and

258-480: Is always the first 256 bytes of memory, hence “zero page”. In native mode, the 65c816 can relocate direct (zero) page anywhere in bank $ 00 (the first 64 KB of memory) by writing the 16-bit starting address into DP . There is a one-cycle access penalty if DP is not set to an exact page boundary, that is, if the value in DP is not $ xx00 , where xx is the most-significant byte. The current mode of operation

301-574: Is available from WDC in 40 pin PDIP , PLCC44 , or 44-pin TQFP packaging, as an MCU through the W65C265, and as IP cores for ASIC integration (for example Winbond 's W55V9x series of TV Edutainment ICs ). WDC 65c816 features: The 65C816 has two operating modes: "emulation mode", in which the 16-bit operations are invisible—the index registers are forced to eight bits—and the chip appears to be very similar to

344-494: Is no longer produced. In 1981, Bill Mensch , founder and CEO of WDC, began development of the 65C02 with his production partners, primarily Rockwell Semiconductor and Synertek . The primary goal of the 65C02 effort was to move from the original 6502's NMOS process to the CMOS process, which would allow it to run at much lower power levels, somewhere between 1 ⁄ 10 and 1 ⁄ 20 at any given clock speed. Also desired

387-469: Is no programmatic means by which PB can be directly changed. During a data fetch or store cycle, DB is prepended to a 16-bit data address to form the 24-bit effective address at which data will be accessed. This processor characteristic makes it possible to sanely execute 6502 or 65c02 code that uses 16-bit addresses to reference data elements. Unlike PB , DB can be changed under program control, something that might be done to access data beyond

430-460: Is prepended to the program counter ( PC ) to form the 24-bit effective address. Should PC "wrap" (return to zero), PB will not be incremented. Hence a program is bounded by the limits of the bank in which it is executing. Implied by this memory model is that branch and subroutine targets must be in the same bank as the instruction making the branch or call, unless "long" jumps or subroutine calls are used to execute code in another bank. There

473-416: Is sometimes called 16-bit because of the way it handles basic arithmetic. The instruction set was based on 32-bit numbers and the internal registers were 32 bits wide, so by common definitions, the 68000 is a 32-bit design. Internally, 32-bit arithmetic is performed using two 16-bit operations, and this leads to some descriptions of the system as 16-bit, or "16/32". Such solutions have a long history in

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516-410: Is stored in the emulation ( e ) bit. Having already added the new x and m bits to the previous set of six flags in the status register ( SR ), there were not enough bits left to hold the new mode bit. Instead, a unique solution was used in which the mode bit was left "invisible", unable to be directly accessed. The XCE (e X change C arry with E mulation) instruction exchanges the value of

559-608: The XBA instruction. There is no corresponding operation for the index registers ( X and Y ), whose MSBs are locked at $ 00 . Upon being switched to native mode, the MSB of X and Y will be zero, and the B -accumulator will be unchanged. If the m bit in SR is cleared, the B -accumulator will be "ganged" to the A -accumulator to form a 16-bit register (called the C -accumulator). A load/store or arithmetic/logical operation involving

602-403: The x flag and bit 5 becomes the m flag. These bits control whether or not the index registers ( x ) and accumulator/memory ( m ) are 8-bit or 16-bit in size. Zeros in these bits set 16-bit sizes, ones set 8-bit sizes. These bits are locked at ones when the processor is powered on or reset, but become changeable when the processor is switched to native mode. In native mode operation,

645-451: The 386SX , which is a 32-bit processor with 32-bit ALU and internal 32-bit data paths with a 16-bit external bus and 24-bit addressing of the processor it replaced. In the context of IBM PC compatible and Wintel platforms, a 16-bit application is any software written for MS-DOS , OS/2 1.x or early versions of Microsoft Windows which originally ran on the 16-bit Intel 8088 and Intel 80286 microprocessors . Such applications used

688-456: The 816 signifies that the MPU has selectable 8- and 16-bit register sizes. In addition to the availability of 16-bit registers, the W65C816S extends memory addressing to 24 bits , supporting up to 16 megabytes of random-access memory . It has an enhanced instruction set and a 16-bit stack pointer , as well as several new electrical signals for improved system hardware management. At reset ,

731-628: The Intel 80286 , the WDC 65C816 , and the Zilog Z8000 . The Intel 8088 was binary compatible with the Intel 8086, and was 16-bit in that its registers were 16 bits wide, and arithmetic instructions could operate on 16-bit quantities, even though its external bus was 8 bits wide. 16-bit processors have been almost entirely supplanted in the personal computer industry, and are used less than 32-bit (or 8-bit) CPUs in embedded applications. The Motorola 68000

774-513: The integer representation used. With the two most common representations, the range is 0 through 65,535 (2 − 1) for representation as an ( unsigned ) binary number , and −32,768 (−1 × 2 ) through 32,767 (2 − 1) for representation as two's complement . Since 2 is 65,536, a processor with 16-bit memory addresses can directly access 64 KB (65,536 bytes) of byte-addressable memory. If a system uses segmentation with 16-bit segment offsets, more can be accessed. The MIT Whirlwind ( c. 1951)

817-517: The zero page , improving speed. This sort of difference between internal register size and external address size remained in the 1980s, although often reversed, as memory costs of the era made a machine with 32-bit addressing, 2 or 4 GB, a practical impossibility. For example, the 68000 exposed only 24 bits of addressing on the DIP , limiting it to a still huge (for the era) 16 MB. A similar analysis applies to Intel's 80286 CPU replacement, called

860-607: The 1960s, especially on minicomputer systems. Early 16-bit computers ( c. 1965–70) include the IBM 1130 , the HP 2100 , the Data General Nova , and the DEC PDP-11 . Early 16-bit microprocessors , often modeled on one of the mini platforms, began to appear in the 1970s. Examples ( c. 1973–76) include the five-chip National Semiconductor IMP-16 (1973), the two-chip NEC μCOM-16 (1974),

903-523: The 6502 then in use in the Apple II but with the ability to address more memory, and to load and store 16 bit words. The result was the 65C816, finished in March 1984, with samples provided to both Apple and Atari in the second half of the year and full release in 1985. Mensch was aided during the design process by his sister Kathryn, who was responsible for part of the device's layout. The same process also led to

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946-472: The 6502, with the same cycle timings for the opcodes; and "native mode", which exposes all new features. The CPU automatically enters emulation mode when it is powered on or reset, which allows it to replace a 65(C)02, assuming one makes the required circuit changes to accommodate the different pin layout. The most obvious change to the 65C816 when running in native mode is the expansion of the various registers from 8-bit to 16-bit sizes. This enhancement affects

989-539: The 6502. The 65c816 makes use of two 8-bit registers, the data bank register ( DB ) and the program bank register ( PB ), to set bits 16-23 of the address, effectively generating 24-bit addresses. In both cases, 'bank' refers to a contiguous 64 KB segment of memory that is bounded by the address range $ xx0000-$ xxFFFF , where xx is the bank address, that is, bits 16-23 of the effective address. Both DB and PB are initialized to $ 00 at power-on or reset. During an opcode or operand fetch cycle, PB

1032-419: The 65C802, which was identical inside to the 65C816. Both were produced on the same fabrication lines and diverged only during the last metalization stages when the chip was being connected to the external pins. In the 65C802, those pins had the same layout as the original 6502, which allowed it to be used as a drop-in replacement while still allowing the 16-bit processing of the CPU to be used. However, as it used

1075-477: The PDIP40 W65C816S is not pin-compatible with any other 6502 family MPU. The W65C802 or 65802 is completely software-compatible with the 65C816, but is electrically-compatible with the 6502 and 65C02. Hence the 65C802 could be used as a drop-in replacement in most systems equipped with a 6502 or 65C02. However, the 65C802 cannot emit a 24-bit address, which limits it to a 64 KB address space. The 65C802

1118-476: The W65C816S starts in "emulation mode", meaning it substantially behaves as a 65C02. Thereafter, the W65C816S may be switched to "native mode" with a two instruction sequence, causing it to enable all enhanced features, yet still maintain a substantial degree of backward compatibility with most 65C02 software. However, unlike the PDIP40 version of the 65C02, which is a pin-compatible replacement for its NMOS ancestor,

1161-401: The accumulator ( A ), the X and Y index registers , and the stack pointer ( SP ). It does not affect the program counter ( PC ), which has always been 16-bit. When running in native mode, two bits in the status register change their meaning. In the original 6502, bits 4 and 5 were not used, although bit 4 is referred to as the break ( b ) flag. In native mode, bit 4 becomes

1204-459: The accumulator and index registers may be set to 16- or 8-bit sizes at the programmer’s discretion by using the REP and SEP instructions to manipulate the m and x status register bits. This feature gives the programmer the ability to perform operations on either word- and byte-size data. As the accumulator and index register sizes are independently settable, it is possible, for example, to have

1247-405: The accumulator is set to 16 bits, will affect two contiguous bytes of memory, not one and will consume more clock cycles than when the accumulator is set to eight bits. Similarly, all arithmetic and logical operations will be 16-bit operations. The other major change to the system while running in native mode is that the memory model is expanded to a 24-bit format from the original 16-bit format of

1290-478: The accumulator or memory will be a 16-bit operation—two bus cycles are required to fetch/store a 16-bit value. If the x bit in SR is cleared, both index registers will be set to 16 bits. If used to index an address, e.g., LDA SOMEWHERE,X , the 16-bit value in the index register will be added to the base address to form the effective address. If the m bit in SR is set, the accumulator will return to being an 8-bit register and subsequent operations on

1333-427: The accumulator set to eight bits and the index registers set to 16 bits, giving the programmer the ability to manipulate individual bytes over a 64KB range without having to perform pointer arithmetic. When register sizes are set to 16 bits, a memory access will fetch or store two contiguous bytes at the rate of one byte per clock cycle. Hence a read-modify-write instruction, such as ROR <addr> , when used while

Toshiba T1100 - Misplaced Pages Continue

1376-411: The accumulator, with a few exceptions, will be 8-bit operations. The B -accumulator will retain the value it had when the accumulator was set to 16 bits. The exceptions are the instructions that transfer the direct page register ( DP ) and stack pointer ( SP ) to/from the accumulator. These operations are always 16 bits wide in native mode, regardless of the condition of the m bit in SR . If

1419-495: The computer field, with various designs performing math even one bit at a time, known as "serial arithmetic", while most designs by the 1970s processed at least a few bits at a time. A common example is the Data General Nova, which was a 16-bit design that performed 16-bit math as a series of four 4-bit operations. 4-bits was the word size of a widely available single-chip ALU and thus allowed for inexpensive implementation. Using

1462-516: The definition being applied to the 68000, the Nova would be a 4-bit computer, or 4/16. Not long after the introduction of the Nova, a second version was introduced, the SuperNova, which included four of the 4-bit ALUs running in parallel to perform math 16 bits at a time and therefore offer higher performance. This was invisible to the user and the programs, which always used 16-bit instructions and data. In

1505-413: The emulation bit with the carry ( c ) bit, bit 0 in SR . For instance, if one wants to enter native mode after the processor has started up, one would use CLC to clear the carry bit, and then XCE to write it to the emulation bit. Returning to 65c02 emulation mode uses SEC followed by XCE . Internally, the 65c816 is a fully 16-bit design. The m and x bits in SR determine how

1548-481: The limits of 16-bit addressing. Also, DB will temporarily increment if an address is indexed beyond the limits of the bank currently in DB . DB is ignored if a 24-bit address is specified as the operand to a data fetch/store instruction, or if the effective address is on direct (zero) page or the hardware stack . In the latter case, an implied bank $ 00 is used to generate the effective address. A further addition to

1591-410: The mid-to-late 1980s to the early 1990s. In the 1990s, both the 65C816 and 65C02 were converted to a fully static core , which made it possible to completely stop the processor's Ø2 clock without loss of register contents. This feature, along with the use of asynchronous static RAM , made it possible to produce designs that used minimal power when in a standby state. As of April 2024 , the W65C816S

1634-469: The original pinout it had only 16 addressing pins, and could therefore only access 64 KB of external memory. Typically, when hardware manufacturers designed a project from the ground up, they used the 65C816 rather than the 65C802, resulting in the latter being withdrawn from production. Apple subsequently integrated the 65C816 into the Apple IIGS computer. The basic 65C816 design was second-sourced by VLSI Technology , GTE , Sanyo and others from

1677-410: The register set is the 16-bit direct page register ( DP ), which sets the base address for what was formerly called the zero page , but now referred to as direct page . Direct page addressing uses an 8-bit address, which results in faster access than when a 16- or 24-bit address is used. Also, some addressing modes that offer indirection are only possible on direct page. In the 65(c)02, the direct page

1720-507: The three-chip Western Digital MCP-1600 (1975), and the five-chip Toshiba T-3412 (1976). Early single-chip 16-bit microprocessors ( c. 1975–76) include the Panafacom MN1610 (1975), National Semiconductor PACE (1975), General Instrument CP1600 (1975), Texas Instruments TMS9900 (1976), Ferranti F100-L , and the HP BPC . Other notable 16-bit processors include the Intel 8086 ,

1763-437: The user registers (accumulator and index) appear to the rest of the system. Upon reset, the 65c816 starts in 6502 emulation mode, in which m and x are locked to 1 . Hence the registers are locked to eight-bit size. The most significant byte (MSB) of the accumulator (the B -accumulator) is not directly accessible but can be swapped with the least significant byte (LSB) of the accumulator (the A -accumulator) by using

Toshiba T1100 - Misplaced Pages Continue

1806-443: Was quite possibly the first-ever 16-bit computer. It was an unusual word size for the era; most systems used six-bit character code and used a word length of some multiple of 6-bits. This changed with the effort to introduce ASCII , which used a 7-bit code and naturally led to the use of an 8-bit multiple which could store a single ASCII character or two binary coded decimal digits. The 16-bit word length thus became more common in

1849-643: Was the ability to raise the maximum supported clock speed. The 65C02 design addressed chip errata present in the NMOS 6502 (e.g., the infamous JMP (<addr>) bug) and introduced new instructions and new addressing modes for some existing instructions. Development of the W65C816S commenced in 1982 after Mensch consulted with Apple Computer on a new version of the Apple II series of personal computers that would, among other things, have improved graphics and sound. Apple wanted an MPU that would be software compatible with

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