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27-473: SGPIO was developed as an engineering collaboration between American Megatrends Inc, at the time makers of back-planes, and LSI-Logic in 2004. SGPIO was later published by the SFF committee as specification SFF-8485 . The SGPIO signal consists of 4 electrical signals; it typically originates from a host bus adapter (HBA). iPass connectors (Usually SFF-8087 or SFF-8484) carry both SAS/SATA electrical connections between

54-444: A Fibre Channel interface card. In this case, it allows devices in a Fibre Channel storage area network to communicate data between each other – it may connect a server to a switch or storage device, connect multiple storage systems, or connect multiple servers. Fibre Channel HBAs are available for open systems , computer architectures, and buses, including PCI and SBus (obsolete today). Each Fibre Channel HBA has

81-450: A host controller , host adapter or host bus adapter ( HBA ) connects a computer system bus which acts as the host system to other network and storage devices. The terms are primarily used to refer to devices for connecting SCSI , SAS , NVMe , Fibre Channel and SATA devices. Devices for connecting to FireWire , USB and other devices may also be called host controllers or host adapters. Host adapters can be integrated in

108-404: A host system and a peripheral SCSI device or storage system. These adapters manage service and task communication between the host and target. Typically a device driver , linked to the operating system , controls the host adapter itself. In a typical parallel SCSI subsystem, each device has assigned to it a unique numerical ID. As a rule, the host adapter appears as SCSI ID 7, which gives it

135-760: A large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD, which allows CPLDs to be used for " boot loader " functions, before handing over control to other devices not having their own permanent program storage. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory. CPLDs were an evolutionary step from even smaller devices that preceded them: PLAs (first shipped by Signetics ) and PALs . These in turn were preceded by standard logic products, which offered no programmability and were used to build logic functions by physically wiring several standard logic chips (or hundreds of them) together (usually with wiring on

162-445: A new SGPIO frame is indicated by SLoad being high at a rising edge of a clock after having been low for at least 5 clock cycles. The following 4 falling clock edges after a start condition is used to carry a 4-bit value from the HBA to the back-plane; the definition of this value is proprietary and varies between system vendors. This line carries 3 bits of data from the HBA to the backplane:

189-672: A unique World Wide Name (WWN), which is similar to an Ethernet MAC address in that it uses an OUI assigned by the IEEE . However, WWNs are longer (8 bytes). There are two types of WWNs on a HBA; a node WWN (WWNN), which is shared by all ports on a host bus adapter, and a port WWN (WWPN), which is unique to each port. There are HBA models of different speeds: 1 Gbit/s, 2 Gbit/s, 4 Gbit/s, 8 Gbit/s, 10 Gbit/s, 16 Gbit/s, 20 Gbit/s and 32 Gbit/s. The major Fibre Channel HBA manufacturers are QLogic and Broadcom . As of mid-2009, these vendors shared approximately 90% of

216-426: Is a programmable logic device with complexity between that of PALs and FPGAs , and architectural features of both. The main building block of the CPLD is a macrocell , which contains logic implementing disjunctive normal form expressions and more specialized logic operations. Some of the CPLD features are in common with PALs : Other features are in common with FPGAs : The most noticeable difference between

243-563: Is a similar technology from the aspect of connection options. HBAs can be created using a single connector to connect both SAS and SATA devices. Major SAS/SATA adapter manufacturers are Promise Technologies, Adaptec , HP , QLogic , Areca, LSI and ATTO Technology . External Serial ATA (eSATA) disk enclosures and drives are available in the consumer computing market, but not all SATA-compatible motherboards and disk controllers include eSATA ports. As such, adapters to connect eSATA devices to ports on an internal SATA bus are available. In

270-660: Is advantageous to quickly update the LEDs on a backplane after cables are removed and re-inserted, while others send data only when there is a need to update the LED pattern. SGPIO and the SGPIO spec. is generally adopted and implemented in products from most major HBA and storage controller vendors such as LSI , Intel , Adaptec , Nvidia , Broadcom , Marvell Technology Group and PMC-Sierra . Most products shipping with support for SAS and SATA drives support this standard. The SGPIO spec calls for

297-465: Is connected, an HBA can detect the presence of a back-plane by the second or third bit of the SDataIn being driven low. The SDataIn and SdataOut then repeats with 3 clocks per drive until the last drive is reached, and the cycle starts over again. There are varieties in how the SGPIO bus is implemented between vendors of HBAs and storage controllers - some vendors will send a continuous stream of data which

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324-571: Is not implemented on them – sampling of the 4-bit lines using GPIOs 100 kHz bit operations is too slow for many low-cost microcontrollers to handle whilst handling LED and other functions simultaneously. The length of the bit stream varies between HBA or storage controller; some vendors will stop the bit-stream when reaching the desired drive, while others will clock it all the way through. Some SAS-expander's bit streams may be as long as 108 (36×3) bits. The safest implementation which ensures compatibility between all HBA and storage controller vendors

351-592: Is to use an ASIC , specifically, a combination of a microcontroller core with a hardware SGPIO interface; this concept was patented in 2006 by AMI and implemented in a series of backplane controller chips named the MG9071 , MG9072 , MG9077 , and MG9082 . These chips will receive 1 or 2 SGPIO streams and drive LEDs accordingly; the latest chip from AMI, the MG9077 , can be configured by pull-up and pull-down resistors to adopt to 16 different configurations of SGPIO buses and drive

378-451: Is transferred by devices on the bus pulling the lines to ground (GND) using an open collector transistor or open drain FET . The SGPIO bus has a dedicated clock line driven by the initiator (its maximum clock rate is 100 kHz), although many implementations use slower ones (typically 48 kHz). This line is synchronous to the clock and is used to indicate the start of a new frame of data;

405-593: The mainframe field, the terms host adapter or host bus adapter were traditionally not used. A similar goal was achieved since the 1960s with channel I/O, a separate processor that can access main memory independently, in parallel with CPU (like later DMA in personal computer field), and that executes its own I/O-dedicated programs when pointed to such by the controlling CPU. Protocols used by channel I/O to communicate with peripheral devices include ESCON and newer FICON . Complex programmable logic device A complex programmable logic device ( CPLD )

432-545: The HBA and the hard drives as well as the 4 SGPIO signals. A backplane is a circuit board with connectors and power circuitry into which hard drives are attached; they can have multiple slots, each of which can be populated with a hard drive. Typically the back-plane is equipped with LEDs which by their color and activity, indicate the slot's status; typically, a slot's LED will emit a particular color or blink pattern to indicate its current status. Although many hardware vendors define their own proprietary LED blinking pattern,

459-438: The HBA, referred to as the initiator and ends at a back-plane , referred to as the target . If a back-plane (or target ) is not present the HBA may still drive the bus without any harm to the system; if one does exist, it can communicate back to the HBA using the 4th wire. The SGPIO bus is an open collector bus with 2.0 kΩ pull-up resistors located at the HBA and the back-plane – as on any open collector bus information

486-405: The LEDs accordingly. Since the availability of these chips from AMI, major OEMs including NEC , Hitachi , Supermicro , IBM , Sun Microsystems , and others are using them on their back-planes to receive the SGPIO streams from a variety of HBA vendors and on-board controller chips to consistently drive LEDs with a pre-determined blinking pattern. Host bus adapter In computer hardware

513-522: The common standard for SGPIO interpretation and LED blinking pattern can be found in the IBPI specification. On back-planes, vendors use typically 2 or 3 LEDs per slot – in both implementations a green LED indicates presence and/or activity – for back-planes with 2 LEDs per slot, the second LED indicates Status whereas in back-planes with 3 LEDs the second and third indicate Locate and Fail . The SGPIO bus consists of 4 signal lines and originates at

540-431: The component that allows a computer to talk to a peripheral bus is host adapter . A proper disk controller only allows a disk to talk to the same bus. SAS or serial-attached SCSI is the current connectivity to replace the previous generation parallel-attached SCSI (PAS) devices. Ultra320 was the highest level of parallel SCSI available, but SAS has since replaced it as the highest-performing SCSI technology. SATA

567-500: The first bit typically carries activity ; the second bit carries locate ; and the third bit carries fail . A low value for the first bit indicates no activity and a high value indicates activity . This line is used by the back-plane and indicates some condition on the back-plane back to the HBA. The first bit being high commonly indicates the presence of a drive. The two following bits are typically unused, and driven low. Because this line would be high for all 3 bits when no backplane

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594-524: The highest priority on the SCSI bus (priority descends as the SCSI ID descends; on a 16-bit or "wide" bus, ID 8 has the lowest priority, a feature that maintains compatibility with the priority scheme of the 8-bit or "narrow" bus). The host adapter usually assumes the role of SCSI initiator , in that it issues commands to other SCSI devices. A computer can contain more than one host adapter, which can greatly increase

621-433: The market. Other manufacturers include Agilent , ATTO , and Brocade . HBA is also known to be interpreted as High Bandwidth Adapter in cases of Fibre Channel controllers. The term host channel adapter ( HCA ) is usually used to describe InfiniBand interface cards. ATA host adapters are integrated into motherboards of most modern PCs . They are often improperly called disk controllers . The correct term for

648-400: The motherboard or be on a separate expansion card . The term network interface controller (NIC) is more often used for devices connecting to computer networks, while the term converged network adapter can be applied when protocols such as iSCSI or Fibre Channel over Ethernet allow storage and network functionality over the same physical connection. A SCSI host adapter connects

675-461: The number of SCSI devices available. Major SCSI adapter manufacturers are HP , ATTO Technology , Promise Technology, Adaptec , and LSI Corporation . LSI, Adaptec, and ATTO offer PCIe SCSI adapters which fit in Apple Mac, on Intel PCs, and low-profile motherboards which lack SCSI support due to the inclusion of SAS and/or SATA connectivity. The term host bus adapter (HBA) may be used to refer to

702-424: The target to turn off all indicators when SClock, SLoad and SDataOut have been high for 64 ms; in practice this is not consistently followed by all vendors. Also, in some vendors' implementations the clock may be halted sporadically or stopped during or between cycles. Another – rather impractical – variation between vendors is the state in which the clock is left after a cycle. The idea behind this specification

729-425: Was to be able to use low cost CPLDs or microcontrollers on a back-plane to drive LEDs; in practice, it has been found that there are variations in timing and interpretations of the bits between vendors, thus a simple CPLD would only work for a specific implementation thoroughly tested with one product from one vendor. A microcontroller is more applicable for this purpose, although the 4-bit SGPIO interface custom bus

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