In computing , a programmable interrupt controller ( PIC ) is an integrated circuit that helps a microprocessor (or CPU ) handle interrupt requests (IRQs) coming from multiple different sources (like external I/O devices) which may occur simultaneously. It helps prioritize IRQs so that the CPU switches execution to the most appropriate interrupt handler (ISR) after the PIC assesses the IRQs' relative priorities. Common modes of interrupt priority include hard priorities, rotating priorities, and cascading priorities. PICs often allow mapping input to outputs in a configurable way. On the PC architecture PIC are typically embedded into a southbridge chip whose internal architecture is defined by the chipset vendor's standards.
5-661: PICs typically have a common set of registers: interrupt request register (IRR), in-service register (ISR), and interrupt mask register (IMR). The IRR specifies which interrupts are pending acknowledgement, and is typically a symbolic register which can not be directly accessed. The ISR register specifies which interrupts have been acknowledged, but are still waiting for an end of interrupt (EOI). The IMR specifies which interrupts are to be ignored and not acknowledged. A simple register schema such as this allows up to two distinct interrupt requests to be outstanding at one time, one waiting for acknowledgement, and one waiting for EOI. There are
10-472: A number of common priority schemas in PICs including hard priorities, specific priorities, and rotating priorities. Interrupts may be either edge triggered or level triggered . There are a number of common ways of acknowledging an interrupt has completed when an EOI is issued. These include specifying which interrupt completed, using an implied interrupt which has completed (usually the highest priority pending in
15-550: The ISR), and treating interrupt acknowledgement as the EOI. One of the best known PICs, the 8259A , was included in the x86 PC. In modern times, this is not included as a separate chip in an x86 PC, but rather as part of the motherboard's southbridge chipset. In other cases, it has been replaced by the newer Advanced Programmable Interrupt Controllers which support more interrupt outputs and more flexible priority schemas. More information on
20-644: The Intel APIC can be found in the IA-32 Intel Architecture Software Developer's Manual, Volume 3A: System Programming Guide, Part 1, Chapter 10 , freely available on the Intel website. End of interrupt An end of interrupt ( EOI ) is a computing signal sent to a programmable interrupt controller (PIC) to indicate the completion of interrupt processing for a given interrupt . Interrupts are used to facilitate hardware signals sent to
25-458: The processor that temporarily stop a running program and allow a special program, an interrupt handler, to run instead. An EOI is used to cause a PIC to clear the corresponding bit in the in-service register (ISR), and thus allow more interrupt requests (IRQs) of equal or lower priority to be generated by the PIC. EOIs may indicate the interrupt vector implicitly or explicitly. An explicit EOI vector
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