The Osborne Vixen is a "luggable" portable computer announced by the Osborne Computer Corporation in November 1984, as a follow-up to their Osborne 1 and Osborne Executive system.
73-429: The Vixen has a 4 MHz Zilog Z80 microprocessor with 64 KB dynamic random-access memory (DRAM) and 4 KB EPROM . It has a 7-inch diagonal amber display that can show 24 lines by 80 columns of memory mapped video. It uses two 400 KB disk drives, utilizing double-density double-sided 5.25" diskettes . As a luggable, it weighs about 18 pounds. Contemporary advertising pointed out that it could fit under
146-593: A MOS Technology 8502 . Zilog was later producing a low-power Z80 suitable for the growing laptop computer market of the early 1980s. Intel produced a CMOS 8085 (80C85) used in battery-powered portable computers, such as the Kyocera -designed laptop from April 1983, also sold by Tandy (as TRS-80 Model 100 ), Olivetti, and NEC. In following years, however, CMOS versions of the Z80 (from both Zilog and Japanese manufacturers) would dominate this market as well, in products such as
219-654: A 16-bit address register HL. In the 8080, this pairing was added to the BC and DE pairs as well, while HL was generalized to allow use as a 16-bit accumulator, not just an address register. The 8080 also introduced immediate 16-bit data for BC, DE, HL, and SP loads. Furthermore, direct 16-bit copying between HL and memory was now possible, using a direct address. The Z80 orthogonalized this further by making all 16-bit register pairs, including IX and IY, more general purpose, as well as allowing 16-bit copying directly to and from memory for all of these pairs. The 16-bit IX and IY registers in
292-476: A European second-source manufacturer SGS . The design was also copied by several Japanese, Eastern European and Soviet manufacturers. This won the Z80 acceptance in the world market since large companies like NEC , Toshiba , Sharp , and Hitachi started to manufacture the device (or their own Z80-compatible clones or designs). The Z80 continued to be used in embedded systems for decades after its introduction, with ongoing advancements. The latest addition to
365-402: A byte and two T-states for each occurrence. This naturally makes the index register unavailable for any other use, or else the need to constantly reload it would negate its efficiency. Zilog eZ80 The Zilog eZ80 is an 8-bit microprocessor designed by Zilog as an updated version of the company's first product, the highly-successful Zilog Z80 . The eZ80 is binary compatible with
438-405: A copyright on their assembly mnemonics, a new assembly syntax had to be developed for the Z80. This time a more systematic approach was used: These principles made it straightforward to find names and forms for all new Z80 instructions, as well as orthogonalizations of old ones, such as LD BC,1234 . Apart from naming differences, and despite a certain discrepancy in basic register structure,
511-473: A day later, Faggin and Ungermann were kicking around ideas based on "integrated logic" when Ungermann said "how about Zilog?" Faggin immediately agreed, stating they could say it was the "last word in integrated logic". When they met the next day and both immediately recalled it, the company had its name. The first samples were returned from Mostek on March 9, 1976. By the end of the month, they had also completed an assembler -based development system . Some of
584-500: A high-level design, adding several concepts of his own. In particular, he used his experience on NEC minicomputers to add the concept of two sets of processor registers so they could quickly respond to interrupts . Ungerman began the development of a series of related controllers and peripheral chips that would complement the design. Through this period, Shima developed a legendary reputation for being able to convert logic concepts into physical design in realtime; while discussing
657-462: A low-cost product like this would not be able to compete with a design from a company with its own production lines, like Intel. They then began considering a more complex microprocessor instead, initially known as the Super 80, with the main feature being its use of a +5 V bus instead of the more common −5, +5 and 12 V used by designs like the 8080. The new design was intended to be compatible with
730-458: A method using only the 8080-model registers. The Z80 also introduced a new signed overflow flag and complemented the fairly simple 16-bit arithmetics of the 8080 with dedicated instructions for signed 16-bit arithmetics. The 8080-compatible registers AF, BC, DE, HL are duplicated as a separate register file in the Z80, where the processor can quickly (four t-states, the least possible execution time for any Z80 instruction) switch from one bank to
803-455: A proposed feature, he would often interrupt and state how much room that would take on the chip and veto its addition if it was too large. The first pass at the design was complete by April 1975. Shima had completed a logic layout by the beginning of May. A second version of the logic design was issued on August 7 and the bus details by September 16. Tape-out was completed in November and converting
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#1732877136611876-422: A regular encoding (common with the 8080) is that each of the 8-bit registers can be loaded from themselves (e.g. LD A,A ). This is effectively a NOP . New block transfer instructions can move up to 64 kilobytes from memory to memory or between memory and I/O peripheral ports. Block instructions LDIR and LDDR ( l oa d , i ncrement/ d ecrement, r epeat) use HL to point to the source address, DE to
949-501: A relative address ( JR instead of JP ) using a signed 8-bit displacement. Only the zero and carry flags can be tested for these new two-byte JR instructions. (All 8080 jumps and calls, conditional or not, are three-byte instructions.) A two-byte instruction specialized for program looping is also new to the Z80: DJNZ ( d ecrement j ump if n on- z ero) takes a signed 8-bit displacement as an immediate operand. The B register
1022-518: A system not using interrupts) it can be used as simply another 8-bit data register. The instructions LD A,R and LD A,I affect the Z80 flags register, unlike all the other LD (load) instructions. The Sign (bit 7) and Zero (bit 6) flags are set according to the data loaded from the Refresh or Interrupt source registers. For both instructions, the Parity/Overflow flag (bit 2) is set according to
1095-544: A total of $ 10 million for the entire industry being spent in all of 1975 (equivalent to $ 57 million in 2023). Someone from Exxon contacted the still-unnamed company, and arranged a meeting that eventually led to them providing an initial $ 500,000 funding in June 1975 (equivalent to $ 2.8 million in 2023). With funding being discussed, and a design to be built, Shima joined in February 1975. Shima immediately set about producing
1168-428: A variable base address (as in recursive stack frames ) and can also reduce code size by removing the need for multiple short instructions using non-indexed registers. However, although they may save speed in some contexts when compared to long/complex "equivalent" sequences of simpler operations, they incur a lot of additional CPU time (e.g., 19 T-states to access one indexed memory location vs. as little as 11 to access
1241-521: A week in order to meet the tight schedule given by the financial investors. The Z80 offered many improvements over the 8080: The Z80 took over from the 8080 and its offspring, the 8085 , in the processor market and became one of the most popular and widely used 8-bit CPUs. Some organizations such as British Telecom remained loyal to the 8085 for embedded applications, owing to their familiarity with it and to its on-chip serial interface and interrupt architecture. Likewise, Zenith Data Systems paired
1314-542: Is 11 times as fast as in the original). The original Z80-compatible 16-bit register configuration is supported. The eZ80 also supports direct continuous addressing of 16 MB of memory without a memory management unit , by extending most registers (HL, BC, DE, IX, IY, SP, and PC) from 16 to 24 bits. In order to do so, the CPU has a full 24-bit address mode called ADL mode. In ADL mode, all Z80 16-bit registers are extended to 24 bits with additional upper 8-bit registers. For example,
1387-604: Is an 8-bit microprocessor designed by Zilog that played an important role in the evolution of early computing. Launched in 1976 and software-compatible with the Intel 8080 , it offered a compelling alternative due to its better integration and increased performance. As well as the 8080's seven registers and flags register, the Z80 had an alternate register set that duplicated them, two 16-bit index registers and additional instructions including bit manipulation and block copy/search. Initially intended for use in embedded systems like
1460-550: Is decremented, and if the result is nonzero, then program execution jumps relative to PC; the flags remain unaltered. To perform an equivalent loop on an 8080 requires separate DEC and conditional jump (to a two-byte absolute address) instructions (totalling four bytes), and the DEC alters the flag register. The index register (IX/IY, often abbreviated XY) instructions can be useful for accessing data organised in fixed heterogenous structures (such as records ) or at fixed offsets relative
1533-510: Is in context unless carefully commented. Thus it is advisable that exchange instructions be used directly and in short discrete code segments. The Zilog Z280 instruction set includes JAF and JAR instructions which jump to a destination address if the alternate registers are in context (thus officially recognizing this programming complication). As on the 8080, 8-bit registers are typically paired to provide 16-bit versions. The 8080 compatible registers are: The new registers introduced with
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#17328771366111606-587: Is often referred to as the "alternate register set" (by some, the "primed" register file since the apostrophe character is used to denote them in assembler source code and the Zilog documentation). This emphasizes that only one set is addressable at any time. However, the 8-bit accumulator A with its flag register F is bifurcated from the "general purpose" register pairs HL, DE and BC. This is accomplished with two separate instructions used to swap their accessibilities: EX AF,AF' exchanges only register pair AF with AF', while
1679-751: Is similar to the original Z80, including the bus request/acknowledge pins, and adds four integrated chip selects. Versions are available with on-chip flash memory and on-chip zero wait-state SRAM (up to 256 KB flash memory and 16 KB SRAM) but there are also external buses on all models. The eZ80 family includes several variants offering different levels of integration. These single-chip computers retain an external address and data bus so they can function as general-purpose microprocessors despite their focus on specific applications. The eZ80Acclaim! line integrates up to 128 KB of flash memory and 8 KB of SRAM, operating at speeds up to 20 MHz. The eZ80AcclaimPlus! adds an Ethernet controller and TCP/IP stack to
1752-551: Is the ZX81 , which lets it keep track of character positions on the TV screen by triggering an interrupt at wrap around (by connecting INT to A6). The interrupt vector register , I , is used for the Z80 specific mode 2 interrupts (selected by the IM 2 instruction). It supplies the high byte of the base address for a 128-entry table of service routine addresses which are selected via an index sent to
1825-414: Is used as the byte counter. The Z80 can input and output any register to an I/O port using register C to designate the port. (The 8080 only performs I/O through the accumulator A, using a direct port address specified in the instruction; a self-modifying code technique is required to use a variable 8080 port address.) The last group of block instructions perform a CP compare operation between
1898-561: The EXX instruction exchanges the three general purpose register pairs HL, DE and BC with their alternates HL', DE' and BC'. Thus the accumulator A can interact independently with any of the general purpose 8-bit registers in the alternate (or primed) register file, or, if HL' contains a pointer to memory, some byte there (DE' and BC' can also transfer 8-bit data between memory and accumulator A). This can become confusing for programmers because after executing EX AF,AF' or EXX what were previously
1971-718: The Amstrad NC100 , Cambridge Z88 and Tandy's own WP-2. Perhaps a key to the initial success of the Z80 was the built-in DRAM refresh, at least in markets such as CP/M and other office and home computers. (Most Z80 embedded systems use static RAM that do not need refresh.) It may also have been its minimalistic two-level interrupt system, or conversely, its general multi-level daisy-chain interrupt system useful in servicing multiple Z80 IO chips. These features allowed systems to be built with less support hardware and simpler circuit board layouts. However, others claim that its popularity
2044-577: The CP/M operating system and Intel's PL/M compiler for 8080 (as well as its generated code), would run unmodified on the new Z80 CPU. Masatoshi Shima designed most of the microarchitecture as well as the gate and transistor levels of the Z80 CPU, assisted by a small number of engineers and layout people. CEO Federico Faggin was actually heavily involved in the chip layout work, together with two dedicated layout people. According to Faggin, he worked 80 hours
2117-657: The Game Boy and TI-83 series . The Z80 was the brainchild of Federico Faggin , a key figure behind the creation of the Intel 8080. After leaving Intel in 1974, Faggin co-founded Zilog with Ralph Ungermann . The Z80 was released in July 1976. With the revenue from the Z80, the company built its own chip factories . Zilog licensed the Z80 to the US-based Synertek and Mostek , which had helped them with initial production, as well as to
2190-406: The 8080); the four remaining codes are used extensively as opcode prefixes : CB and ED enable extra instructions, and DD or FD select IX+d or IY+d respectively (in some cases without displacement d) in place of HL. This scheme gives the Z80 a large number of permutations of instructions and registers; Zilog categorizes these into 158 different "instruction types", 78 of which are the same as those of
2263-430: The 8080, as the Z80 sometimes indicates signed overflow where the 8080 would indicate parity, possibly causing the logic of some practical 8080 software to fail on the Z80. ) This new overflow flag is used for all new Z80-specific 16-bit operations ( ADC , SBC ) as well as for 8-bit arithmetic operations, while the 16-bit operations inherited from the 8080 ( ADD , INC , DEC ) do not affect it. Also, bit 1 of
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2336-495: The 8080, but add many of the nice features of the Motorola 6800 , including index registers and improved interrupts . While still being set up, the industry newsletter Electronic News heard of them and published a story on the newly formed company. This attracted the attention of Exxon Enterprises, Exxon 's high-tech investment arm. At the time, in the midst of the recession, there was very little venture capital available, with
2409-549: The 8080, the Z80's combination of compatibility, affordability, and superior performance propelled it to widespread adoption in video game systems and home computers during the late 1970s and early 1980s, fueling the personal computing revolution. Products it was used in include the Osborne 1 , Radio Shack TRS-80 , ColecoVision , ZX Spectrum and the Pac-Man cabinet; in later years it remained used in portables, best known for use in
2482-645: The 8085 with the 16-bit Intel 8088 in its first MS-DOS computer, the Zenith Z-100 , despite having previous experience with its pioneering Z80-based Heathkit H89 and Zenith Z-89 products. However, other computers were made integrating the Z80 with other CPUs: the Radio Shack TRS-80 Model ;16 with a Motorola 68000 , the DEC Rainbow with an 8088, and the Commodore ;128 with
2555-464: The CPU during an interrupt acknowledge cycle; this index is simply the low byte part of the pointer to the tabulated indirect address pointing to the service routine. The pointer identifies a particular peripheral chip or peripheral function or event, where the chips are normally connected in a so-called daisy chain for priority resolution. Like the refresh register, this register has also sometimes been used creatively; in interrupt modes 0 and 1 (or in
2628-447: The HL register pair is extended with an uppermost register called HLU. The resulting 24-bit multi-byte register is collectively accessed by its old name, HL. The upper registers cannot be accessed individually. The processor has a 24-bit ALU arithmetic logic unit and overlapped processing of several instructions (the three-stage pipeline) which are the two primary reasons for its speed. Unlike
2701-412: The Intel 8080 (allowing operation of all 8080 programs on a Z80). The Zilog documentation further groups instructions into the following categories (most from the 8080, others entirely new like the block and bit instructions, and others 8080 instructions with more versatile addressing modes, like the 16-bit loads, I/O, rotates/shifts and relative jumps): No explicit multiply instructions are available in
2774-581: The Osborne Computer Corporation. An earlier system also called "Vixen" was never released. Due to technical problems with prototypes and the corporate bankruptcy, by the time the CP/M Vixen was introduced, it had already been made obsolete by MS-DOS IBM PC compatibles . A last ditch effort to design and market a fully IBM PC compatible produced three prototypes, but too late to save the company from bankruptcy. Zilog Z80 The Zilog Z80
2847-461: The Z80 and 8086 syntax are virtually isomorphic for a large portion of instructions. Only quite superficial similarities (such as the word MOV, or the letter X, for extended register) exist between the 8080 and 8086 assembly languages, although 8080 programs can be translated to 8086 assembly language by translator programs . The Z80 uses 252 out of the available 256 codes as single byte opcodes ("root instruction" most of which are inherited from
2920-567: The Z80 are fairly conventional, ultimately based on the register structure of the Datapoint 2200 . The Z80 was designed as an extension of the Intel 8080, created by the same engineers, which in turn was an extension of the 8008 . The 8008 was basically a PMOS implementation of the TTL-based CPU of the Datapoint 2200. The 2200 design allowed 8-bit registers H and L (High and Low) to be paired into
2993-469: The Z80 are primarily intended as base address-registers, where a particular instruction supplies a constant offset that is added to the previous values, but they are also usable as 16-bit accumulators, among other things. A limitation is that all operand references involving IX or IY require an extra instruction prefix byte, adding at least four clock cycles over the timing of an instruction using HL instead; this sometimes makes using IX or IY less efficient than
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3066-424: The Z80 are: The refresh register , R , increments each time the CPU fetches an opcode (or an opcode prefix, which internally executes like a 1-byte instruction) and has no simple relationship with program execution. This has sometimes been used to generate pseudorandom numbers in games, and also in software protection schemes. It has also been employed as a "hardware" counter in some designs; an example of this
3139-518: The Z80 family is the eZ80 , which was offered alongside successor chips. Zilog announced the discontinuation of the Z80 in April 2024 after nearly five decades of production. At Fairchild Semiconductor , and later at Intel , physicist and engineer Federico Faggin had been working on fundamental transistor and semiconductor manufacturing technology. He also developed the basic design methodology used for memories and microprocessors at Intel and led
3212-450: The Z80 support and peripheral ICs were under development at this point, and many of them were launched during the following year. Among them were the Z80 CTC (counter/timer), Z80 DMA (direct memory access), Z80 DART (dual asynchronous receiver–transmitter), Z80 SIO (synchronous communication controller), and Z80 PIO (parallel input/output). The Z80 was officially launched in July 1976. One of
3285-508: The Z80, but operating almost three times faster at the same clock frequency . The eZ80 has a three-stage pipeline: fetch, decode, and execute. When an instruction changes the program counter , it flushes the instructions that the CPU is currently processing. Available at up to 50 MHz (2004), the performance is comparable to a Z80 clocked at 150 MHz if fast memory is used (i.e. no wait states for opcode fetches, for data, or for I/O) or even higher in some applications (a 16-bit addition
3358-467: The Z80. However, this would likely be erroneous code on the 8080, as DAA was defined for addition only on that processor. The Z80 has six new LD instructions that can load the DE, BC, and SP register pairs from memory, and load memory from these three register pairs—unlike the 8080. As on the 8080, load instructions do not affect the flags (except for the special-purpose I and R register loads). A result of
3431-464: The alternate (primed) registers are now the main registers, and vice versa. The only way for the programmer to tell which set(s) are in context (while "playing computer" while scrutinizing the assembler source text, or worse, poring over code with a debugger) is to trace where each register swap is made at each point in the program. Obviously if many jump and calls are made within these code segments it can quickly become difficult to tell which register file
3504-452: The byte at (HL) and the accumulator A. Register pair DE is not used. The repeating versions CPIR and CPDR only terminate if BC goes to zero or a match is found. HL is left pointing to the byte after ( CPIR ) or before ( CPDR ) the matching byte. If no match is found the Z ;flag is reset. There are non-repeating versions CPI and CPD . Unlike the 8080, the Z80 can jump to
3577-498: The current state of the IFF2 flip-flop. Although the Z80 is generally considered an eight-bit CPU, it has a four-bit ALU , so calculations are done in two steps. The first Intel 8008 assembly language was based on a very simple (but systematic) syntax inherited from the Datapoint 2200 design. This original syntax was later transformed into a new, somewhat more traditional, assembly language form for this same original 8008 chip. At about
3650-415: The design directly. Faggin thought this would mean they could never compete even if they set up their own lines, and the agreement fell through. He then turned to Mostek, who agreed to a term of exclusivity while Zilog got their lines set up, and were eventually given the second source agreement. After considering many names for the new company, and finding them so unmemorable they could not recall them even
3723-479: The design. Sometime later, Shima was told by an engineer within NEC that the traps had delayed their copying efforts by six months. The successful launch allowed Faggin and Ungermann to approach Exxon looking for funding to build their own fab. The company agreed, and Zilog built a production line very rapidly. This allowed them to capture about 60 to 70% of the total market for Z80 sales. With their own line running, Mostek
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#17328771366113796-566: The destination address, and BC as a byte counter. Bytes are copied from source to destination, the pointers are incremented or decremented, and the byte counter is decremented until BC reaches zero. Non-repeating versions LDI and LDD move a single byte and bump the pointers and byte counter, which if it becomes zero resets the P/V ;flag. Corresponding memory-to-I/O instructions INIR , INDR , OTIR , OTDR , INI , IND , OUTI and OUTD operate similarly, except that B, not BC,
3869-481: The first customers was a buyer who, unknown to Zilog, worked for NEC. At the time, the Japanese electronics companies were well known for taking US chip designs and producing them without a license. The Zilog team had worried about this, and Faggin had come up with the idea of adding transistors that would be subtly modified to operate differently than a visual inspection would suggest. Shima added six of these "traps" around
3942-506: The flags register (a spare bit on the 8080) is used as a flag N that indicates whether the last arithmetic instruction executed was a subtraction or addition. The Z80 version of the DAA instruction (decimal adjust accumulator for BCD arithmetic) checks the N ;flag and behaves accordingly, so a (hypothetical) subtraction followed later by DAA will yield a different result on an old 8080 than on
4015-562: The formerly independent sections under the direction of Les Vadasz, further diluting the microprocessor's place in the company. That year, the 1973–1975 recession reached a peak and Intel laid off a number of employees. All of this led to Faggin becoming restless, and he invited Ungermann out for drinks and asked if he would be interested in starting their own company. Ungermann immediately agreed, and as he had less to do at Intel, left in August or September, followed by Faggin, whose last day at Intel
4088-631: The introductory 2.5 MHz , via the well known 4 MHz (Z80A), up to 6 MHz (Z80B) and 8 MHz (Z80H). The NMOS version has been produced as a 10 MHz part since the late 1980s. CMOS versions were developed with specified upper frequency limits ranging from 4 MHz up to 20 MHz for the version sold today. The CMOS versions allowed low-power standby with internal state retained, having no lower frequency limit. The fully compatible derivatives HD64180 / Z180 and eZ80 are currently specified for up to 33 MHz and 50 MHz, respectively. The programming model and register set of
4161-456: The older Z280 and Z380 it does not have (or need) a cache memory. Instead, it is intended to work with fast SRAM directly as main memory (as this had become much cheaper). Nor does it have the multiplexed bus of the Z280, making it as easy to work with (interface to) as the original Z80 and Z180, and equally predictable when it comes to exact execution times. The chip has a memory interface that
4234-426: The original Z80 (being 1 clock slower than in the 8080/8085); nonetheless, they are about twice as fast as performing the same calculations using 8-bit operations, and equally important, they reduce register usage. It was not uncommon for programmers to "poke" different offset displacement bytes (which were typically calculated dynamically) into indexed instructions; this is an example of self-modifying code , which
4307-407: The original Z80, though registers A and HL can be multiplied by powers of two with ADD A,A and ADD HL,HL instructions (similarly IX and IY also). Shift instructions can also multiply or divide by powers of two. Different sizes and variants of additions, shifts, and rotates have somewhat differing effects on flags because most of the flag-changing properties of the 8080 were copied. However,
4380-483: The other; a feature useful for speeding up responses to single-level, high-priority interrupts. A similar feature was present in the 2200, but was never implemented at Intel. The dual register-set is very useful in the embedded role, as it improves interrupt handling performance, but found widespread use in the personal computer role as an additional set of general registers for complex code like floating-point arithmetic or home computer games. The duplicate register file
4453-418: The parity flag bit P of the 8080 (bit 2) is called P/V (parity/overflow) in the Z80 as it serves the additional purpose of a twos complement overflow indicator, a feature lacking in the 8080. Arithmetic instructions on the Z80 set it to indicate overflow rather than parity, while bitwise instructions still use it as a parity flag. (This introduces a subtle incompatibility of the Z80 with code written for
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#17328771366114526-404: The popular word processing package; SuperCalc , a spreadsheet; MBASIC , a programming language; Osboard , a graphics and drawing program; TurnKey , a system utility; Media Master , a data interchange program that allowed compatibility with over "200 other computers"; and Desolation , a game. The Vixen was also known as the Osborne 4 . It was developed and released after the bankruptcy of
4599-535: The same memory using HL and INC to point to the next). Thus, for simple or linear accesses of data, use of IX and IY tend to be slower and occupy more memory. Still, they may be useful in cases where the "main" registers are all occupied, by removing the need to save/restore registers. Their officially undocumented 8-bit halves (see below) can be especially useful in this context, for they incur less slowdown than their 16-bit parents. Similarly, instructions for 16-bit additions are not particularly fast (11 clocks) in
4672-517: The same time, the new assembly language was also extended to accommodate the additional addressing modes in the more advanced Intel 8080 chip (the 8008 and 8080 shared a language subset without being binary compatible ; however, the 8008 was binary compatible with the Datapoint 2200). In this process, the mnemonic L , for LOAD , was replaced by various abbreviations of the words LOAD , STORE and MOVE , intermixed with other symbolic letters. The mnemonic letter M , for memory (referenced by HL),
4745-473: The seat in an airplane , with dimensions of 12 5 ⁄ 8 by 16 1 ⁄ 4 by 6 1 ⁄ 4 inches (321 by 413 by 159 mm). When it was released, the Vixen had a retail price of $ 1298. Customers also had the option of purchasing an external 10 megabyte hard disk for $ 1495. The Vixen used version 2.2 of the CP/M operating system. It was also bundled with a number of software packages: WordStar ,
4818-438: The tape into a production mask required two more months. Faggin had already started looking for a production partner. By this time, Synertek and Mostek had both set up the depletion-mode production lines that could be used to produce the design. Having talked to Synertek previously, Faggin approached them first. However, the president of Synertek demanded that the company be given a second source license, allowing them to sell
4891-409: The value should be used as a memory address (as mentioned below), while the 8086 syntax uses brackets instead of ordinary parentheses for this purpose. Both Z80 and 8086 use the + sign to indicate that a constant is added to a base register to form an address. Note that the 8086 is not a complete superset of the Z80. BX is the only 8086 register pair that can be used as a pointer. Because Intel claimed
4964-478: The work on the Intel 4004 , the Intel 8080 and several other ICs. Masatoshi Shima was the principal logic and transistor-level designer of the 4004 and the 8080 under Faggin's supervision, while Ralph Ungermann was in charge of custom integrated circuit design. In early 1974, Intel viewed their microprocessors not so much as products to be sold on their own but as a way to sell more of their main products, static RAM and ROM . A reorganization placed many of
5037-407: Was Halloween 1974. When Shima heard, he asked to come to the new company as well, but having no actual product design or money, they told him to wait. The newly formed and unnamed company initially began designing a single-chip microcontroller called the 2001. They met with Synertek to discuss fabrication on their lines, and when Faggin began to understand the costs involved it became clear that
5110-454: Was due to the duplicated registers that allowed fast context switches or more efficient processing of things like floating-point math compared to 8-bit CPUs with fewer registers. (The Z80 can keep several such numbers internally, using HL'HL, DE'DE and BC'BC as 32-bits registers, avoiding having to access them from slower RAM during computation.) For the original NMOS design, the specified upper clock-frequency limit increased successively from
5183-456: Was given the go-ahead to start sales of their own versions, the MK3880, which provided a second-source for customers which Intel lacked. At the time, a second-source was considered extremely important as a start-up like Zilog might go out of business and leave potential customers stranded. Faggin designed the instruction set to be binary compatible with the 8080 so that most 8080 code, notably
5256-546: Was lifted out from within the instruction mnemonic to become a syntactically freestanding operand , while registers and combinations of registers became very inconsistently denoted; either by abbreviated operands (MVI D, LXI H and so on), within the instruction mnemonic itself (LDA, LHLD and so on), or both at the same time (LDAX B, STAX D and so on). Illustration of four syntaxes, using samples of equivalent, or (for 8086) very similar, load and store instructions. The Z80 syntax uses parentheses around an expression to indicate that
5329-531: Was regular practice on nearly all early 8-bit processors with non- pipelined execution units. The index registers have a parallel instruction to JP (HL) , which is JP (XY) . This is often seen in stack-oriented languages like Forth , which at the end of every Forth word (atomic subroutines comprising the language) must jump unconditionally back to their thread interpreter routines. Typically this jump instruction appears many hundreds of times in an application, and using JP (XY) rather than JP THREAD saves
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