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52-842: PureView cameras have on-chip image processors that perform image scaling with oversampling , allowing additional digital zoom , and reduced noise compared to a typical smartphone camera. Both are combined with xenon flash , a 1080p HD video camera , and high-resolution Zeiss all- aspherical 1-group lenses. Unlike the Nokia 808, the Nokia Lumia 1020 — along with other Lumia PureView smartphone cameras — possesses optical image stabilization , which became standard in Lumia PureView bundling. The Nokia 808 does, however, compensate with its own exclusive camera-complementing media features, such as Micro HDMI TV-out , and built-in video editing. Following

104-516: A communications subsystem to connect, control, direct and interface between these functional modules. An SoC must have at least one processor core , but typically an SoC has more than one core. Processor cores can be a microcontroller , microprocessor (μP), digital signal processor (DSP) or application-specific instruction set processor (ASIP) core. ASIPs have instruction sets that are customized for an application domain and designed to be more efficient than general-purpose instructions for

156-447: A memory hierarchy and cache hierarchy . In the mobile computing market, this is common, but in many low-power embedded microcontrollers, this is not necessary. Memory technologies for SoCs include read-only memory (ROM), random-access memory (RAM), Electrically Erasable Programmable ROM ( EEPROM ) and flash memory . As in other computer systems, RAM can be subdivided into relatively faster but more expensive static RAM (SRAM) and

208-494: A microcontroller , microprocessor or perhaps several processor cores with peripherals like a GPU , Wi-Fi and cellular network radio modems or one or more coprocessors . Similar to how a microcontroller integrates a microprocessor with peripheral circuits and memory, an SoC can be seen as integrating a microcontroller with even more advanced peripherals . Compared to a multi-chip architecture, an SoC with equivalent functionality will have reduced power consumption as well as

260-653: A netlist describing the design as a physical circuit and its interconnections. These netlists are combined with the glue logic connecting the components to produce the schematic description of the SoC as a circuit which can be printed onto a chip. This process is known as place and route and precedes tape-out in the event that the SoCs are produced as application-specific integrated circuits (ASIC). SoCs must optimize power use , area on die , communication, positioning for locality between modular units and other factors. Optimization

312-399: A semiconductor foundry . This process is called functional verification and it accounts for a significant portion of the time and energy expended in the chip design life cycle , often quoted as 70%. With the growing complexity of chips, hardware verification languages like SystemVerilog , SystemC , e , and OpenVera are being used. Bugs found in the verification stage are reported to

364-484: A 3D package chip with two dies stacked vertically. Toshiba called it "semi-embedded DRAM" at the time, before later calling it a stacked "chip-on-chip" (CoC) solution. In April 2007, Toshiba commercialized an eight-layer 3D chip package, the 16   GB THGAM embedded NAND flash memory chip, which was manufactured with eight stacked 2   GB NAND flash chips. The same month, U.S. patent 7,923,830 ("Package-on-package secure module having anti-tamper mesh in

416-515: A certain level of computational performance , but power is limited in most SoC environments. SoC designs are optimized to minimize waste heat output on the chip. As with other integrated circuits , heat generated due to high power density are the bottleneck to further miniaturization of components. The power densities of high speed integrated circuits, particularly microprocessors and including SoCs, have become highly uneven. Too much waste heat can damage circuits and erode reliability of

468-527: A chip consists of both the hardware , described in § Structure , and the software controlling the microcontroller, microprocessor or digital signal processor cores, peripherals and interfaces. The design flow for an SoC aims to develop this hardware and software at the same time, also known as architectural co-design. The design flow must also take into account optimizations ( § Optimization goals ) and constraints. Most SoCs are developed from pre-qualified hardware component IP core specifications for

520-1005: A circuit is the integral of power consumed with respect to time, and the average rate of power consumption is the product of current by voltage . Equivalently, by Ohm's law , power is current squared times resistance or voltage squared divided by resistance : P = I V = V 2 R = I 2 R {\displaystyle P=IV={\frac {V^{2}}{R}}={I^{2}}{R}} SoCs are frequently embedded in portable devices such as smartphones , GPS navigation devices , digital watches (including smartwatches ) and netbooks . Customers want long battery lives for mobile computing devices, another reason that power consumption must be minimized in SoCs. Multimedia applications are often executed on these devices, including video games, video streaming , image processing ; all of which have grown in computational complexity in recent years with user demands and expectations for higher- quality multimedia. Computation

572-434: A controller and memory. This yields better electrical performance of devices, since shorter routing of interconnections between circuits yields faster signal propagation and reduced noise and cross-talk. There are several key differences between stacked-die and stacked-package products. The main financial benefit of package on a package is that the memory device is decoupled from the logic device. Therefore this gives PoP all

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624-866: A different processor. For further discussion of multi-processing memory issues, see cache coherence and memory latency . SoCs include external interfaces , typically for communication protocols . These are often based upon industry standards such as USB , Ethernet , USART , SPI , HDMI , I²C , CSI , etc. These interfaces will differ according to the intended application. Wireless networking protocols such as Wi-Fi , Bluetooth , 6LoWPAN and near-field communication may also be supported. When needed, SoCs include analog interfaces including analog-to-digital and digital-to-analog converters , often for signal processing . These may be able to interface with different types of sensors or actuators , including smart transducers . They may interface with application-specific modules or shields. Or they may be internal to

676-439: A discrete application processor). High-performance SoCs are often paired with dedicated and physically separate memory and secondary storage (such as LPDDR and eUFS or eMMC , respectively) chips that may be layered on top of the SoC in what is known as a package on package (PoP) configuration, or be placed close to the SoC. Additionally, SoCs may use separate wireless modems (especially WWAN modems). An SoC integrates

728-461: A manner independent of time scales, which are typically specified in HDL. Other components can remain software and be compiled and embedded onto soft-core processors included in the SoC as modules in HDL as IP cores . Once the architecture of the SoC has been defined, any new hardware elements are written in an abstract hardware description language termed register transfer level (RTL) which defines

780-406: A package ( PoP ) is an integrated circuit packaging method to vertically combine discrete logic and memory ball grid array (BGA) packages. Two or more packages are installed atop each other, i.e. stacked, with a standard interface to route signals between them. This allows higher component density in devices, such as mobile phones , personal digital assistants (PDA), and digital cameras , at

832-454: A package technique tries to combine the benefits of traditional packaging with the benefits of die-stacking techniques, while avoiding their drawbacks. Traditional packaging places each die in its own package, a package designed for normal PCB assembly techniques that place each package directly on the PCB side-by-side. The 3D die-stacking system in package (SiP) techniques stacks multiple die in

884-486: A power source while needing to maintain autonomous function, and often are limited in power use by a high number of embedded SoCs being networked together in an area. Additionally, energy costs can be high and conserving energy will reduce the total cost of ownership of the SoC. Finally, waste heat from high energy consumption can damage other circuit components if too much heat is dissipated, giving another pragmatic reason to conserve energy. The amount of energy used in

936-609: A single package, which has several advantages and also some disadvantages compared to traditional PCB assembly. In embedded PoP techniques, chips are embedded in a substrate on the bottom of the package. This PoP technology enables smaller packages with shorter electrical connections and is supported by companies such as Advanced Semiconductor Engineering (ASE). The most obvious benefit is motherboard space savings. PoP uses much less PCB area, almost as little as stacked-die packages. Electrically, PoP offers benefits by minimizing track length between different interoperating parts, such as

988-464: A smaller semiconductor die area. This comes at the cost of reduced replaceability of components. By definition, SoC designs are fully or nearly fully integrated across different component modules . For these reasons, there has been a general trend towards tighter integration of components in the computer hardware industry , in part due to the influence of SoCs and lessons learned from the mobile and embedded computing markets. SoCs are very common in

1040-495: A software integrated development environment . SoCs components are also often designed in high-level programming languages such as C++ , MATLAB or SystemC and converted to RTL designs through high-level synthesis (HLS) tools such as C to HDL or flow to HDL . HLS products called "algorithmic synthesis" allow designers to use C++ to model and synthesize system, circuit, software and verification levels all in one high level language commonly known to computer engineers in

1092-429: A specific type of workload. Multiprocessor SoCs have more than one processor core by definition. The ARM architecture is a common choice for SoC processor cores because some ARM-architecture cores are soft processors specified as IP cores . SoCs must have semiconductor memory blocks to perform their computation, as do microcontrollers and other embedded systems . Depending on the application, SoC memory may form

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1144-578: Is an integrated circuit that integrates most or all components of a computer or electronic system . These components usually include an on-chip central processing unit (CPU), memory interfaces, input/output devices and interfaces, and secondary storage interfaces, often alongside other components such as radio modems and a graphics processing unit (GPU) – all on a single substrate or microchip. SoCs may contain digital and also analog , mixed-signal and often radio frequency signal processing functions (otherwise it may be considered on

1196-492: Is more demanding as expectations move towards 3D video at high resolution with multiple standards , so SoCs performing multimedia tasks must be computationally capable platform while being low power to run off a standard mobile battery. SoCs are optimized to maximize power efficiency in performance per watt: maximize the performance of the SoC given a budget of power usage. Many applications such as edge computing , distributed processing and ambient intelligence require

1248-780: Is necessarily a design goal of SoCs. If optimization was not necessary, the engineers would use a multi-chip module architecture without accounting for the area use, power consumption or performance of the system to the same extent. Common optimization targets for SoC designs follow, with explanations of each. In general, optimizing any of these quantities may be a hard combinatorial optimization problem, and can indeed be NP-hard fairly easily. Therefore, sophisticated optimization algorithms are often required and it may be practical to use approximation algorithms or heuristics in some cases. Additionally, most SoC designs contain multiple variables to optimize simultaneously , so Pareto efficient solutions are sought after in SoC design. Oftentimes

1300-890: The bottlenecks of bus-based networks. Networks-on-chip have advantages including destination- and application-specific routing , greater power efficiency and reduced possibility of bus contention . Network-on-chip architectures take inspiration from communication protocols like TCP and the Internet protocol suite for on-chip communication, although they typically have fewer network layers . Optimal network-on-chip network architectures are an ongoing area of much research interest. NoC architectures range from traditional distributed computing network topologies such as torus , hypercube , meshes and tree networks to genetic algorithm scheduling to randomized algorithms such as random walks with branching and randomized time to live (TTL). Many SoC researchers consider NoC architectures to be

1352-529: The mobile computing (as in smart devices such as smartphones and tablet computers ) and edge computing markets. In general, there are three distinguishable types of SoCs: SoCs can be applied to any computing task. However, they are typically used in mobile computing such as tablets, smartphones, smartwatches, and netbooks as well as embedded systems and in applications where previously microcontrollers would be used. Where previously only microcontrollers could be used, SoCs are rising to prominence in

1404-487: The FPGA RTL that make signals available for observation. This is used to debug hardware, firmware and software interactions across multiple FPGAs with capabilities similar to a logic analyzer. In parallel, the hardware elements are grouped and passed through a process of logic synthesis , during which performance constraints, such as operational frequency and expected signal delays, are applied. This generates an output known as

1456-737: The SoC, if needed. Popular time sources are crystal oscillators and phase-locked loops . SoC peripherals including counter -timers, real-time timers and power-on reset generators. SoCs also include voltage regulators and power management circuits. SoCs comprise many execution units . These units must often send data and instructions back and forth. Because of this, all but the most trivial SoCs require communications subsystems . Originally, as with other microcomputer technologies, data bus architectures were used, but recently designs based on sparse intercommunication networks known as networks-on-chip (NoC) have risen to prominence and are forecast to overtake bus architectures for SoC design in

1508-1228: The SoC, such as if an analog sensor is built in to the SoC and its readings must be converted to digital signals for mathematical processing. Digital signal processor (DSP) cores are often included on SoCs. They perform signal processing operations in SoCs for sensors , actuators , data collection , data analysis and multimedia processing. DSP cores typically feature very long instruction word (VLIW) and single instruction, multiple data (SIMD) instruction set architectures , and are therefore highly amenable to exploiting instruction-level parallelism through parallel processing and superscalar execution . SP cores most often feature application-specific instructions, and as such are typically application-specific instruction set processors (ASIP). Such application-specific instructions correspond to dedicated hardware functional units that compute those instructions. Typical DSP instructions include multiply-accumulate , Fast Fourier transform , fused multiply-add , and convolutions . As with other computer systems, SoCs require timing sources to generate clock signals , control execution of SoC functions and provide time context to signal processing applications of

1560-524: The acquisition of the Nokia Devices & Services division by Microsoft , the U.S. software company acquired the PureView name and trademark, but not the related imaging technology, which remained with Nokia, who, as a result, licensed it to Microsoft. Since Microsoft's ownership, the technology has only been used in their late-2015 flagship Lumia 950 . In late August 2018, HMD Global reportedly acquired

1612-427: The circuit behavior, or synthesized into RTL from a high level language through high-level synthesis. These elements are connected together in a hardware description language to create the full SoC design. The logic specified to connect these components and convert between possibly different interfaces provided by different vendors is called glue logic . Chips are verified for validation correctness before being sent to

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1664-435: The circuit over time. High temperatures and thermal stress negatively impact reliability, stress migration , decreased mean time between failures , electromigration , wire bonding , metastability and other performance degradation of the SoC over time. In particular, most SoCs are in a small physical area or volume and therefore the effects of waste heat are compounded because there is little room for it to diffuse out of

1716-496: The cost of slightly higher height requirements. Stacks with more than 2 packages are uncommon, due to heat dissipation considerations. Two widely used configurations exist for PoP: During PCB assembly , the bottom package of a PoP stack is placed directly on the PCB, and the other package(s) of the stack are stacked on top. The packages of a PoP stack become attached to each other (and to the PCB) during reflow soldering . The package on

1768-532: The data throughput of the SoC. This is similar to some device drivers of peripherals on component-based multi-chip module PC architectures. Wire delay is not scalable due to continued miniaturization , system performance does not scale with the number of cores attached, the SoC's operating frequency must decrease with each additional core attached for power to be sustainable, and long wires consume large amounts of electrical power. These challenges are prohibitive to supporting manycore systems on chip. In

1820-676: The designer. Traditionally, engineers have employed simulation acceleration, emulation or prototyping on reprogrammable hardware to verify and debug hardware and software for SoC designs prior to the finalization of the design, known as tape-out . Field-programmable gate arrays (FPGAs) are favored for prototyping SoCs because FPGA prototypes are reprogrammable, allow debugging and are more flexible than application-specific integrated circuits (ASICs). With high capacity and fast compilation time, simulation acceleration and emulation are powerful technologies that provide wide visibility into systems. Both technologies, however, operate slowly, on

1872-804: The embedded systems market. Tighter system integration offers better reliability and mean time between failure , and SoCs offer more advanced functionality and computing power than microcontrollers. Applications include AI acceleration , embedded machine vision , data collection , telemetry , vector processing and ambient intelligence . Often embedded SoCs target the internet of things , multimedia, networking, telecommunications and edge computing markets. Some examples of SoCs for embedded applications include: Mobile computing based SoCs always bundle processors, memories, on-chip caches , wireless networking capabilities and often digital camera hardware and firmware. With increasing memory sizes, high end SoCs will often have no memory and flash storage and instead,

1924-425: The future of SoC design because they have been shown to efficiently meet power and throughput needs of SoC designs. Current NoC architectures are two-dimensional. 2D IC design has limited floorplanning choices as the number of cores in SoCs increase, so as three-dimensional integrated circuits (3DICs) emerge, SoC designers are looking towards building three-dimensional on-chip networks known as 3DNoCs. A system on

1976-512: The goals of optimizing some of these quantities are directly at odds, further adding complexity to design optimization of SoCs and introducing trade-offs in system design. For broader coverage of trade-offs and requirements analysis , see requirements engineering . SoCs are optimized to minimize the electrical power used to perform the SoC's functions. Most SoCs must use low power. SoC systems often require long battery life (such as smartphones ), can potentially spend months or years without

2028-431: The hardware elements and execution units , collectively "blocks", described above, together with software device drivers that may control their operation. Of particular importance are the protocol stacks that drive industry-standard interfaces like USB . The hardware blocks are put together using computer-aided design tools, specifically electronic design automation tools; the software modules are integrated using

2080-639: The interconnection delays and maximize the speed at which data is communicated between modules, functional units and memories. In general, optimizing to minimize latency is an NP-complete problem equivalent to the Boolean satisfiability problem . For tasks running on processor cores, latency and throughput can be improved with task scheduling . Some tasks run in application-specific hardware units, however, and even task scheduling may not be sufficient to optimize all software-based tasks to meet timing and throughput constraints. Package on package Package on

2132-482: The late 2010s, a trend of SoCs implementing communications subsystems in terms of a network-like topology instead of bus-based protocols has emerged. A trend towards more processor cores on SoCs has caused on-chip communication efficiency to become one of the key factors in determining the overall system performance and cost. This has led to the emergence of interconnection networks with router -based packet switching known as " networks on chip " (NoCs) to overcome

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2184-471: The low-resolution screen on the 808 PureView made appreciating the camera's capabilities much harder. Nokia was given several awards for the release of its PureView camera, including the TIPA Best Imaging Innovation award in 2012. System on a chip A system on a chip or system-on-chip ( SoC / ˌ ˈ ɛ s oʊ s iː / ; pl. SoCs / ˌ ˈ ɛ s oʊ s iː z / )

2236-588: The memory and flash memory will be placed right next to, or above ( package on package ), the SoC. Some examples of mobile computing SoCs include: In 1992, Acorn Computers produced the A3010, A3020 and A4000 range of personal computers with the ARM250 SoC. It combined the original Acorn ARM2 processor with a memory controller (MEMC), video controller (VIDC), and I/O controller (IOC). In previous Acorn ARM -powered computers, these were four discrete chips. The ARM7500 chip

2288-471: The near future. Historically, a shared global computer bus typically connected the different components, also called "blocks" of the SoC. A very common bus for SoC communications is ARM's royalty-free Advanced Microcontroller Bus Architecture ( AMBA ) standard. Direct memory access controllers route data directly between external interfaces and SoC memory, bypassing the CPU or control unit , thereby increasing

2340-430: The order of MHz, which may be significantly slower – up to 100 times slower – than the SoC's operating frequency. Acceleration and emulation boxes are also very large and expensive at over US$ 1 million. FPGA prototypes, in contrast, use FPGAs directly to enable engineers to validate and test at, or close to, a system's full operating frequency with real-world stimuli. Tools such as Certus are used to insert probes in

2392-519: The ownership of the PureView trademark and related assets not under Nokia ownership. On 24 February 2019, HMD Global , the exclusive licensee of Nokia-branded phones, launched the Nokia 9 PureView at the 2019 Mobile World Congress in Barcelona. On 19 March 2020, HMD Global announced the Nokia 8.3 5G , which is said to feature a 64MP PureView Quad-Camera System with Carl Zeiss Optics. The Nokia X30 5G

2444-633: The risk of catastrophic failure . Due to increased transistor densities as length scales get smaller, each process generation produces more heat output than the last. Compounding this problem, SoC architectures are usually heterogeneous, creating spatially inhomogeneous heat fluxes , which cannot be effectively mitigated by uniform passive cooling . SoCs are optimized to maximize computational and communications throughput . SoCs are optimized to minimize latency for some or all of their functions. This can be accomplished by laying out elements with proper proximity and locality to each-other to minimize

2496-619: The same advantages that traditional packaging has over stacked-die products: Package on a package is also known by other names: In 2001, a Toshiba research team including T. Imoto, M. Matsui and C. Takubo developed a "System Block Module" wafer bonding process for manufacturing 3D integrated circuit (3D IC) packages. The earliest known commercial use of a 3D package-on-package chip was in Sony 's PlayStation Portable (PSP) handheld game console , released in 2004. The PSP hardware includes eDRAM (embedded DRAM ) memory manufactured by Toshiba in

2548-458: The slower but cheaper dynamic RAM (DRAM). When an SoC has a cache hierarchy, SRAM will usually be used to implement processor registers and cores' built-in caches whereas DRAM will be used for main memory . "Main memory" may be specific to a single processor (which can be multi-core ) when the SoC has multiple processors , in this case it is distributed memory and must be sent via § Intermodule communication on-chip to be accessed by

2600-420: The system. Because of high transistor counts on modern devices, oftentimes a layout of sufficient throughput and high transistor density is physically realizable from fabrication processes but would result in unacceptably high amounts of heat in the circuit's volume. These thermal effects force SoC and other chip designers to apply conservative design margins , creating less performant devices to mitigate

2652-566: Was announced on 2 September 2022 with PureView technology, but the ZEISS lens is absent due to HMD Global ending its partnership with Carl Zeiss AG. The X30 features a 50 MP main sensor, which is the same as the Samsung Galaxy S22 . At its initial debut with the Nokia 808 PureView , the PureView camera was acknowledged by critics as one of the most advanced smartphone cameras in the market. Critics also said it made devices bulky and heavy, and that

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2704-709: Was their second-generation SoC, based on the ARM700, VIDC20 and IOMD controllers, and was widely licensed in embedded devices such as set-top-boxes, as well as later Acorn personal computers. Tablet and laptop manufacturers have learned lessons from embedded systems and smartphone markets about reduced power consumption, better performance and reliability from tighter integration of hardware and firmware modules , and LTE and other wireless network communications integrated on chip (integrated network interface controllers ). An SoC consists of hardware functional units , including microprocessors that run software code , as well as

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