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80-469: Transmeta Corporation was an American fabless semiconductor company based in Santa Clara, California . It developed low power x86 compatible microprocessors based on a VLIW core and a software layer called Code Morphing Software . Code Morphing Software (CMS) consisted of an interpreter , a runtime system and a dynamic binary translator . x86 instructions were first interpreted one instruction at

160-454: A 45 nm process). The Efficeon included an integrated Northbridge , while the competing Atom required an external Northbridge chip, reducing much of the Atom's power consumption benefits. The Transmeta Efficeon processor addressed many of Crusoe's shortcomings and showed roughly a 2x real-world improvement over Crusoe. Its die was considerably smaller than Pentium 4 and Pentium M, when compared in

240-405: A basic block . He also developed region scheduling methods to identify parallelism beyond basic blocks. Trace scheduling is such a method, and involves scheduling the most likely path of basic blocks first, inserting compensating code to deal with speculative motions, scheduling the second most likely trace, and so on, until the schedule is complete. Fisher's second innovation was the notion that

320-419: A stealth start-up . The company was largely successful in hiding its ambitions until its official company launch on January 19, 2000. Over 2000 non-disclosure agreements (NDAs) were signed during the stealth period. Throughout Transmeta's first few years, little was known about exactly what it would be offering. Its web site went online in mid 1997 and for approximately two and a half years displayed nothing but

400-495: A VLIW mode. In the VLIW mode, the processor always fetched two instructions and assumed that one was an integer instruction and the other floating-point. The i860's VLIW mode was used extensively in embedded digital signal processor (DSP) applications since the application execution and datasets were simple, well ordered and predictable, allowing designers to fully exploit the parallel execution advantages enabled by VLIW. In VLIW mode,

480-524: A VLIW, the compiler uses heuristics or profile information to guess the direction of a branch. This allows it to move and preschedule operations speculatively before the branch is taken, favoring the most likely path it expects through the branch. If the branch takes an unexpected way, the compiler has already generated compensating code to discard speculative results to preserve program semantics. Vector processor cores (designed for large one-dimensional arrays of data called vectors ) can be combined with

560-459: A hybrid PowerPC and x86 processor. But Transmeta would initially concentrate solely on the extremely low-power x86 market. The ability to quickly update products without a hardware respin was demonstrated in 2002 with an in-the-field upgrade (a download) to enhance CPU performance of the Crusoe based HP Compaq TC1000 tablet PC. It was used again in 2004 when NX bit and SSE3 support were added to

640-412: A key cause of much lower performance for many real-world applications; the simple VLIW core architecture could not compete on computationally intensive applications; and the southbridge interface was limited by its low bandwidth for graphics or other I/O-intensive applications. Some standard benchmarks even failed to run, throwing the claim of full x86 compatibility into doubt. The Efficeon processor

720-703: A much longer opcode (termed very long ) to specify what executes on a given cycle. Examples of contemporary VLIW CPUs include the TriMedia media processors by NXP (formerly Philips Semiconductors), the Super Harvard Architecture Single-Chip Computer (SHARC) DSP by Analog Devices, the ST200 family by STMicroelectronics based on the Lx architecture (designed in Josh Fisher's HP lab by Paolo Faraboschi),

800-454: A one time license fee of $ 25 million. On November 17, Transmeta announced the signing of a definitive agreement to be acquired by Novafora , a digital video processor company based in Santa Clara, California , for $ 255.6 million in cash, subject to adjustments dependent on working capital. The deal was finalized on January 28, 2009, when Novafora announced the completion of its acquisition of Transmeta. Intellectual Venture Funding LLC completed

880-594: A part of a textbook two years before Fisher's seminal paper, but because of the Iron Curtain and because Kartsev's work was mostly military-related it remained largely unknown in the West. Fisher's innovations involved developing a compiler that could target horizontal microcode from programs written in an ordinary programming language . He realized that to get good performance and target a wide-issue machine, it would be necessary to find parallelism beyond that generally within

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960-453: A program, termed out-of-order execution . These three methods all raise hardware complexity. Before executing any operations in parallel, the processor must verify that the instructions have no interdependencies . For example, if a first instruction's result is used as a second instruction's input, then they cannot execute at the same time and the second instruction cannot execute before the first. Modern out-of-order processors have increased

1040-427: A sequence of RISC-like instructions. The compiler analyzes this code for dependence relationships and resource requirements. It then schedules the instructions according to those constraints. In this process, independent instructions can be scheduled in parallel. Because VLIWs typically represent instructions scheduled in parallel with a longer instruction word that incorporates the individual instructions, this results in

1120-544: A small portfolio of patents to Intel as part of the deal. Transmeta also agreed to never manufacture x86 compatible processors again. One significant sore point in the Intel litigation was the payout of approximately $ 34M to three of Transmeta's executives. In late 2008, Intel and Transmeta reached a further agreement to transfer the $ 20 million per year in one lump sum. On August 8, 2008, Transmeta announced that it had licensed its LongRun and low power chip technologies to Nvidia for

1200-503: A standard CDC Aerospace Computer and was used in the Spy in the Sky Satellites in addition to other classified satellite programs. GIM was reluctant to proceed with the next phase of the program, which it deemed to be too technically challenging. The GIM engineers who had worked on the project were encouraged by CDC to form their own company to provide five new custom circuits. This resulted in

1280-575: A technology named Flexible Length Instruction eXtensions (FLIX) that allows multi-operation instructions. The Xtensa C/C++ compiler can freely intermix 32- or 64-bit FLIX instructions with the Xtensa processor's one-operation RISC instructions, which are 16 or 24 bits wide. By packing multiple operations into a wide 32- or 64-bit instruction word and allowing these multi-operation instructions to intermix with shorter RISC instructions, FLIX allows SoC designers to realize VLIW's performance advantages while eliminating

1360-487: A technology obsoleted as it grew more cost-effective to integrate all of the components of a processor (excluding memory) on one chip. Multiflow was too early to catch the following wave, when chip architectures began to allow multiple-issue CPUs. The major semiconductor companies recognized the value of Multiflow technology in this context, so the compiler and architecture were subsequently licensed to most of these firms. A processor that executes every instruction one after

1440-424: A time and profiled, then depending upon the frequency of execution of a code block, CMS would progressively generate more optimized translations. The VLIW core implemented features specifically designed to accelerate CMS and translations. Among the features were support for general speculation, detection of memory aliasing and detection of self modifying x86 code. The combination of CMS and the VLIW core allowed for

1520-580: Is a VLIW microarchitecture. In December 2015, the first shipment of PCs based on VLIW CPU Elbrus-4s was made in Russia. The Neo by REX Computing is a processor consisting of a 2D mesh of VLIW cores aimed at power efficiency. The Elbrus 2000 ( Russian : Эльбрус 2000 ) and its successors are Russian 512-bit wide VLIW microprocessors developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC . When silicon technology allowed for wider implementations (with more execution units) to be built,

1600-477: Is intended to allow higher performance without the complexity inherent in some other designs. The traditional means to improve performance in processors include dividing instructions into sub steps so the instructions can be executed partly at the same time (termed pipelining ), dispatching individual instructions to be executed independently, in different parts of the processor ( superscalar architectures ), and even executing instructions in an order different from

1680-567: Is sometimes distinguished from a pure VLIW architecture, since EPIC advocates full instruction predication, rotating register files, and a very long instruction word that can encode non-parallel instruction groups. VLIWs also gained significant consumer penetration in the graphics processing unit (GPU) market, though both Nvidia and AMD have since moved to RISC architectures to improve performance on non-graphics workloads. ATI Technologies ' (ATI) and Advanced Micro Devices ' (AMD) TeraScale microarchitecture for graphics processing units (GPUs)

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1760-479: Is the code bloat that occurs when one or more execution unit(s) have no useful work to do and thus must execute No Operation NOP instructions. This occurs when there are dependencies in the code and the instruction pipelines must be allowed to drain before later operations can proceed. Since the number of transistors on a chip has grown, the perceived disadvantages of the VLIW have diminished in importance. VLIW architectures are growing in popularity, especially in

1840-937: The FR-V from Fujitsu , the BSP15/16 from Pixelworks , the CEVA-X DSP from CEVA, the Jazz DSP from Improv Systems, the HiveFlex series from Silicon Hive, and the MPPA Manycore family by Kalray. The Texas Instruments TMS320 DSP line has evolved, in its C6000 family, to look more like a VLIW, in contrast to the earlier C5000 family. These contemporary VLIW CPUs are mainly successful as embedded media processors for consumer electronic devices. VLIW features have also been added to configurable processor cores for system-on-a-chip (SoC) designs. For example, Tensilica's Xtensa LX2 processor incorporates

1920-468: The Transmeta Efficeon product line without requiring hardware changes. In the field upgrades were rare in practice due to system hardware vendors not wanting to incur additional customer support costs or spend additional money on QA for the potential upgrades or bug fixes to shipped products they had already closed the revenue books on. Fabless Prior to the 1980s, the semiconductor industry

2000-449: The code bloat of early VLIW architectures. The Infineon Carmel DSP is another VLIW processor core intended for SoC. It uses a similar code density improvement method called configurable long instruction word (CLIW). Outside embedded processing markets, Intel's Itanium IA-64 explicitly parallel instruction computing (EPIC) and Elbrus 2000 appear as the only examples of a widely used VLIW CPU architectures. However, EPIC architecture

2080-402: The compiler (software used to create the final programs) becomes more complex, but the hardware is simpler than in many other means of parallelism. The concept of VLIW architecture, and the term VLIW , were invented by Josh Fisher in his research group at Yale University in the early 1980s. His original development of trace scheduling as a compiling method for VLIW was developed when he

2160-459: The 1990s. Along with the above systems, during the same time (1989–1990), Intel implemented VLIW in the Intel i860 , their first 64-bit microprocessor, and the first processor to implement VLIW on one chip. This processor could operate in both simple RISC mode and VLIW mode: In the early 1990s, Intel introduced the i860 RISC microprocessor. This simple chip had two modes of operation: a scalar mode and

2240-533: The 2009 acquisition by Novafora, Transmeta had moderate success licensing its IP. Licensors for Transmeta technology are Intel (with a perpetual, non-exclusive license to all Transmeta patents and patent applications, including any that Transmeta might acquire before December 31, 2017), Nvidia (with non-exclusive license to Transmeta's LongRun and LongRun2 technologies and other intellectual property), Sony (LongRun2 licensee), Fujitsu (LongRun2 licensee) and NEC (LongRun2 licensee). Founded in 1995, Transmeta began as

2320-500: The CPU guesses wrong, all of these instructions and their context need to be flushed and the correct ones loaded, which takes time. This has led to increasingly complex instruction-dispatch logic that attempts to guess correctly , and the simplicity of the original reduced instruction set computing (RISC) designs has been eroded. VLIW lacks this logic, and thus lacks its energy use, possible design defects, and other negative aspects. In

2400-472: The CPU's internal machine code. Thus, the Transmeta chip is internally a VLIW processor, effectively decoupled from the x86 CISC instruction set that it executes. Intel's Itanium architecture (among others) solved the backward-compatibility problem with a more general mechanism. Within each of the multiple-opcode instructions, a bit field is allocated to denote dependency on the prior VLIW instruction within

2480-538: The Efficeon processor. In 2005, Transmeta increased its focus on licensing its portfolio of microprocessor and semiconductor technologies. After layoffs in 2007, Transmeta made a complete shift away from semiconductor production to IP licensing. In January 2009, the company was acquired by Novafora and the patent portfolio was sold to Intellectual Ventures . Novafora ceased operations in August 2009. Intellectual Ventures licenses

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2560-552: The ICs. These parts were given the designation LSI3201, LSI3202, LSI3203, LSI3204 and LSI3205. Another successful space program completed by LSI/CSI was the upgrade to class S of a Standard Brushless DC Motor Commutator/Controller Chip, LS7262, which was implemented in satellites. In 1994, Jodi Shelton , along with a half a dozen CEOs of fabless companies, established the Fabless Semiconductor Association (FSA) to promote

2640-507: The Internet to see. Crusoe will be cool hardware and software for mobile applications. Crusoe will be unconventional, which is why we wanted to let you know in advance to come look at the entire Web site in January, so that you can get the full story and have access to all of the real details as soon as they are available. Transmeta attempted to staff the company in secret although speculation online

2720-486: The Transmeta IP to other companies on a non-exclusive basis. Transmeta produced two x86 compatible CPU architectures : Crusoe and Efficeon – internal code names were 'Fred' and 'Astro'. These CPUs have appeared in subnotebooks , notebooks , desktops , blade servers , tablet PCs , a personal cluster computer, and a silent desktop, where low power consumption and heat dissipation are of primary importance. Before

2800-700: The VLIW architecture such as in the Fujitsu FR-V microprocessor, further increasing throughput and speed . Cydrome was a company producing VLIW numeric processors using emitter-coupled logic (ECL) integrated circuits in the same timeframe (late 1980s). This company, like Multiflow, failed after a few years. One of the licensees of the Multiflow technology is Hewlett-Packard , which Josh Fisher joined after Multiflow's demise. Bob Rau , founder of Cydrome, also joined HP after Cydrome failed. These two would lead computer architecture research at Hewlett-Packard during

2880-515: The achievement of full x86 compatibility while maintaining performance and reducing power consumption. Transmeta was founded in 1995 by Bob Cmelik , Dave Ditzel , Colin Hunter, Ed Kelly, Doug Laird , Malcolm Wing and Greg Zyner . Its first product, the Crusoe processor, was launched on January 19, 2000. Transmeta went public on November 7, 2000. On October 14, 2003, it launched its second major product,

2960-591: The acquisition of the patent portfolio formerly developed and owned by Transmeta Corporation on February 4, 2009. Due to financial troubles and inability to execute, Novafora collapsed in late July, 2009. Transmeta had a succession of 6 different chief executive officers who ran the company over its lifetime. Among its crew of technologists, Transmeta employed some of the industry's more public figures including Linux founder Linus Torvalds , Linux kernel developer Hans Peter Anvin , Yacc author Stephen C. Johnson , and game developer Dave D. Taylor . Partially because of

3040-466: The birth of the fabless business model . Engineers at new companies began designing and selling integrated circuits (ICs) without owning a fabrication plant. Simultaneously, the foundry industry was established by Dr. Morris Chang with the founding of Taiwan Semiconductor Manufacturing Corporation (TSMC). Foundries became the cornerstone of the fabless model, providing a non-competitive manufacturing partner for fabless companies. The co-founders of

3120-514: The competition. In January 2005, the company announced its first strategic restructuring away from being a semiconductor product company and began to focus on licensing intellectual property. In March 2005, Transmeta announced that it was laying off 68 people while retaining 208 employees. Sony was reported to be a key licensee of Transmeta technology and approximately half of the remaining employees were to work on LongRun2 power optimization technology for Sony. On May 31, 2005, Transmeta announced

3200-473: The compiled programs for the earlier generation would not run on the wider implementations, as the encoding of binary instructions depended on the number of execution units of the machine. Transmeta addressed this issue by including a binary-to-binary software compiler layer (termed code morphing ) in their Crusoe implementation of the x86 architecture. This mechanism was advertised to basically recompile, optimize, and translate x86 opcodes at runtime into

3280-501: The compiler. Compilers of the day were far more complex than those of the 1980s, so the added complexity in the compiler was considered to be a small cost. VLIW CPUs are usually made of multiple RISC-like execution units that operate independently. Contemporary VLIWs usually have four to eight main execution units. Compilers generate initial instruction sequences for the VLIW CPU in roughly the same manner as for traditional CPUs, generating

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3360-450: The complexity of instruction scheduling is moved into the compiler, complexity of hardware can be reduced substantially. A similar problem occurs when the result of a parallelizable instruction is used as input for a branch. Most modern CPUs guess which branch will be taken even before the calculation is complete, so that they can load the instructions for the branch, or (in some architectures) even start to compute them speculatively . If

3440-519: The development and licensing of intellectual property. Subsequently, AMD invested $ 7.5 million in Transmeta, planning to use the company's patent portfolio in energy-efficient technologies. On October 24, 2007, Transmeta announced an agreement to settle its lawsuit against Intel Corporation. Intel agreed to pay $ 150 million upfront and $ 20 million per year for five years to Transmeta in addition to dropping its counterclaims against Transmeta. Transmeta also agreed to license several of its patents and assign

3520-762: The fabless business-model globally. In December 2007, the FSA transitioned to the GSA, the Global Semiconductor Alliance . The organizational transition reflected the role FSA had played as a global organization that collaborated with other organizations to co-host international events. The fabless manufacturing model has been further validated by the conversion of major IDMs to a completely fabless model, including (for example) Conexant Systems , Semtech , and most recently, LSI Logic . Today most major IDMs including Apple Inc. , Infineon and Cypress Semiconductor have adopted

3600-457: The first fabless semiconductor company, LSI Computer Systems, Inc. (LSI/CSI) LSI/CSI, worked together at General Instrument Microelectronics (GIM) in the 1960s. In 1969 GIM was hired to develop three full custom CPU circuits for Control Data Corporation (CDC). These CPU ICs operated at 5 MHz (state of the art at the time) and were incorporated in the CDC Computer 469. The Computer 469 became

3680-648: The following is an instruction for the Super Harvard Architecture Single-Chip Computer (SHARC). In one cycle, it does a floating-point multiply, a floating-point add, and two autoincrement loads. All of this fits in one 48-bit instruction: f12 = f0 * f4, f8 = f8 + f12, f0 = dm(i0, m3), f4 = pm(i8, m9); Since the earliest days of computer architecture, some CPUs have added several arithmetic logic units (ALUs) to run in parallel. Superscalar CPUs use hardware to decide which operations can run in parallel at runtime, while VLIW CPUs use software (the compiler) to decide which operations can run in parallel in advance. Because

3760-455: The following: CDC's Aerospace Computer 469 weighed one pound, consumed a total of 10 watts and ran at 5 MHz. CDC ran a parallel program, developing a chipset of eight similar parts that were to operate at 2.5 MHz with the identical environmental and Class S requirements. CDC had initial difficulties with this project, but eventually awarded another contract to LSI/CSI to manage the processing, inspection, visuals, assembly, and testing of

3840-452: The formation of LSI Computer Systems, Inc. (LSI/CSI) in 1969. The new chips were power-efficient random logic circuits with extremely high circuit densities. These new circuits also operated at 5 MHz. These devices were designated LSI0101, LSI0102, LSI0103, LSI0104, and LSI0105 and were manufactured in compact 40-pin metal flat packs with 0.050 inches (1.3 mm) spacing. In creating the fabless semiconductor industry, LSI/CSI had to do

3920-539: The frequency of execution and other heuristics , CMS would progressively generate more optimized translations. Similar technologies existed in the 1990s: Wabi for Solaris and Linux , FX!32 for Alpha and IA-32 EL for Itanium , open-source DAISY, the Mac 68K emulator for the PowerPC. The Transmeta approach set a much higher bar for x86 compatibility due to its ability to execute all x86 instructions from initial boot up to

4000-400: The hardware resources which schedule instructions and determine interdependencies. In contrast, VLIW executes operations in parallel, based on a fixed schedule, determined when programs are compiled . Since determining the order of execution of operations (including which operations can execute simultaneously) is handled by the compiler, the processor does not need the scheduling hardware that

4080-449: The headcount of the company by 40%. On October 14, 2003, Transmeta announced the Efficeon processor which was claimed to have twice the performance of the original Crusoe CPU at the same frequency. However, performance was still weak relative to the competition and the complexity of the chip had increased significantly. The greater size and power consumption may have diluted a key market advantage Transmeta's chips had previously enjoyed over

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4160-417: The i860 could maintain floating-point performance in the range of 20-40 double-precision MFLOPS; a very high value for its time and for a processor running at 25-50Mhz. In the 1990s, Hewlett-Packard researched this problem as a side effect of ongoing work on their PA-RISC processor family. They found that the CPU could be greatly simplified by removing the complex dispatch logic from the CPU and placing it in

4240-523: The instruction width is 32 bits or fewer. In contrast, one VLIW instruction encodes multiple operations, at least one operation for each execution unit of a device. For example, if a VLIW device has five execution units, then a VLIW instruction for the device has five operation fields, each field specifying what operation should be done on that corresponding execution unit. To accommodate these operation fields, VLIW instructions are usually at least 64 bits wide, and far wider on some architectures. For example,

4320-425: The instructions that saved the result, needing very complex scheduling algorithms. Fisher developed a set of principles characterizing a proper VLIW design, such as self-draining pipelines, wide multi-port register files , and memory architectures . These principles made it easier for compilers to emit fast code. The first VLIW compiler was described in a Ph.D. thesis by John Ellis, supervised by Fisher. The compiler

4400-449: The latest multimedia instructions. The operation of Transmeta's code morphing software is similar to the final optimization pass of a conventional compiler. Considering a fragment of 32-bit x86 code: This is first converted simplistically into native instructions: The optimizer then eliminates common sub-expressions and unnecessary condition code operations and, potentially, applies other optimizations such as loop unrolling : Finally,

4480-414: The optimizer groups individual instructions ("atoms") into long instruction words ("molecules") for the underlying hardware: These two VLIW molecules could potentially execute in fewer cycles than the original instructions could on an x86 processor. Transmeta claimed several technical benefits to this approach: Prior to Crusoe's release, rumors indicated Transmeta was relying on these benefits to develop

4560-480: The other (i.e., a non- pipelined scalar architecture) may use processor resources inefficiently, yielding potential poor performance. The performance can be improved by executing different substeps of sequential instructions simultaneously (termed pipelining ), or even executing multiple instructions entirely simultaneously as in superscalar architectures. Further improvement can be achieved by executing instructions in an order different from that in which they occur in

4640-407: The performance still significantly lagged behind Intel's Pentium M (Banias) and AMD's Mobile Athlon XP . Transmeta processors were in-order very long instruction word (VLIW) cores running a special dynamic binary translation software layer which together implemented compatibility with the x86 architecture. Transmeta trademarked the term "Code Morphing" to describe their technology and referred to

4720-1021: The practice of outsourcing chip manufacturing as a significant manufacturing strategy. The top 5 sales leaders for fabless companies in 2023 were: The top 5 sales leaders for fabless companies in 2020 were: The top 5 sales leaders for fabless companies in 2019 were: The top 5 sales leaders for fabless companies in 2017 were: The top 5 sales leaders for fabless companies in 2013 were: The top 5 sales leaders for fabless companies in 2011 were: The top 5 sales leaders for fabless companies in 2010 were: The top 5 sales leaders for fabless companies in 2003 were: Very long instruction word Very long instruction word ( VLIW ) refers to instruction set architectures that are designed to exploit instruction-level parallelism (ILP). A VLIW processor allows programs to explicitly specify instructions to execute in parallel , whereas conventional central processing units (CPUs) mostly allow programs to specify instructions to execute in sequence only. VLIW

4800-577: The presence of these figures, the industry was constantly abuzz with rumors and ' conspiracy theories ' resulting in excellent press relations . The following charts show the company's revenues, operating expenses, gross profits and net losses from 1996 through 2007. Numbers are in 1000s as per the 10-K reports. The company was once named as the Most important company in Silicon Valley in an Upside magazine editorial but failed to obtain profitability while it

4880-424: The program ( out-of-order execution ). These methods all complicate hardware (larger circuits, higher cost and energy use) because the processor must make all of the decisions internally for these methods to work. In contrast, the VLIW method depends on the programs providing all the decisions regarding which instructions to execute simultaneously and how to resolve conflicts. As a practical matter, this means that

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4960-453: The program instruction stream. These bits are set at compile time , thus relieving the hardware from calculating this dependency information. Having this dependency information encoded in the instruction stream allows wider implementations to issue multiple non-dependent VLIW instructions in parallel per cycle, while narrower implementations would issue a smaller number of VLIW instructions per cycle. Another perceived deficiency of VLIW designs

5040-527: The same process technology. Efficeon's die fabricated in 90 nm is 68 mm, which is 60% of the Pentium 4 in 90 nm, at 112 mm, with both processors possessing a 1 MB L2 cache. The notion of selling a product into a specific thermal envelope was typically not understood by the mass of reviewers, who tended to compare Efficeon to the gamut of x86 microprocessors, regardless of power consumption or application. One such example of this criticism suggests

5120-496: The signing of asset purchase and license agreements with Hong Kong’s Culture.com Technology Limited. The deal fell apart due to delays in obtaining technology export licenses from the US Department of Commerce and the parties announced the termination of the agreements on February 9, 2006. On August 10, 2005, Transmeta announced its first-ever profitable quarter. This was followed by GameSpot ’s March 20, 2006 report that Transmeta

5200-465: The software layer as Code Morphing Software (CMS). Transmeta used reverse body bias to reduce power used by a factor of about 2.5. (A similar technology was used in XScale processors.) Code Morphing Software ( CMS ) is the technology used by Transmeta microprocessors to execute x86 instructions. In broad view, CMS reads x86 instructions and generates instructions for a proprietary VLIW processor, in

5280-412: The style of Shade. CMS translation is much more expensive than Shade's, but produces much higher quality code. CMS also contains an interpreter and simulates both user-mode and system mode operation. Code Morphing Software consisted of an interpreter , a runtime system and a dynamic binary translator . x86 instructions were first interpreted one instruction at a time and profiled, then depending upon

5360-416: The target CPU architecture should be designed to be a reasonable target for a compiler; that the compiler and the architecture for a VLIW processor must be codesigned. This was inspired partly by the difficulty Fisher observed at Yale of compiling for architectures like Floating Point Systems ' FPS164, which had a complex instruction set computing (CISC) architecture that separated instruction initiation from

5440-468: The technology. Transmeta marketed their microprocessor technology as extraordinarily innovative and revolutionary in the low-power market segment. They had hoped to be both power and performance leaders in the x86 space but initial reviews of Crusoe indicated the performance fell significantly short of projections. Also, while Crusoe was in development, Intel and AMD significantly ramped up speeds and began to address concerns about power consumption. So Crusoe

5520-494: The text, "This web page is not yet here." On November 12, 1999, a cryptic comment in the HTML appeared: Yes, there is a secret message, and this is it: Transmeta's policy has been to remain silent about its plans until it had something to demonstrate to the world. On January 19, 2000, Transmeta is going to announce and demonstrate what Crusoe processors can do. Simultaneously, all of the details will go up on this Web site for everyone on

5600-484: The three methods described above require. Thus, VLIW CPUs offer more computing with less hardware complexity (but greater compiler complexity) than do most superscalar CPUs. This is also complementary to the idea that as many computations as possible should be done before the program is executed, at compile time. In superscalar designs, the number of execution units is invisible to the instruction set. Each instruction encodes one operation only. For most superscalar designs,

5680-661: Was vertically integrated . Semiconductor companies owned and operated their own silicon-wafer fabrication facilities and developed their own process technology for manufacturing their chips. These companies also carried out the assembly and testing of their own chips. As with most technology-intensive industries, the silicon manufacturing process presents high barriers to entry into the market, especially for small start-up companies. But integrated device manufacturers (IDMs) had excess production capacity. This presented an opportunity for smaller companies, relying on IDMs, to design but not manufacture silicon. These conditions underlay

5760-408: Was Transmeta's second-generation 256-bit VLIW processor design. Like the Crusoe (a 128-bit VLIW architecture), Efficeon stressed computational efficiency, low power consumption, and a low thermal footprint. A 2004-model 1.6-GHz Transmeta Efficeon (manufactured using a 90 nm process) had roughly the same performance and power characteristics as a 1.6-GHz Intel Atom from 2008 (manufactured using

5840-411: Was a chip vendor. Transmeta received a total of $ 969M in funding during its lifetime. Crusoe was the first family of microprocessors from Transmeta, named after the literary character Robinson Crusoe . Transmeta lost much credibility and endured significant criticism due to the large discrepancies between projected performance and power consumption and the actual results. Although power consumption

5920-536: Was a graduate student at New York University . Before VLIW, the notion of prescheduling execution units and instruction-level parallelism in software was well established in the practice of developing horizontal microcode . Before Fisher the theoretical aspects of what would be later called VLIW were developed by the Soviet computer scientist Mikhail Kartsev based on his Sixties work on military-oriented M-9 and M-10 computers. His ideas were later developed and published as

6000-423: Was infringing Transmeta's patents by making and selling a variety of microprocessor products, including at least Intel's Pentium III, Pentium 4, Pentium M, Core and Core 2 product line. On February 7, 2007, Transmeta shut down its engineering services division terminating 75 employees in the process. This was concurrent with an announcement that the company would no longer develop and sell hardware and would focus on

6080-564: Was named Bulldog, after Yale's mascot. Fisher left Yale in 1984 to found a startup company, Multiflow , along with cofounders John O'Donnell and John Ruttenberg. Multiflow produced the TRACE series of VLIW minisupercomputers , shipping their first machines in 1987. Multiflow's VLIW could issue 28 operations in parallel per instruction. The TRACE system was implemented in a mix of medium-scale integration (MSI), large-scale integration (LSI), and very large-scale integration (VLSI) , packaged in cabinets,

6160-519: Was not uncommon. Information gradually came out of the company suggesting it was working on a very long instruction word (VLIW) design that translated x86 code into its own native VLIW code. On January 19, 2000, Transmeta held a launch event at Villa Montalvo in Saratoga, California and announced to the world that it had been working on an x86 compatible dynamic binary translation processor named Crusoe. It also released an 18-page whitepaper describing

6240-569: Was rapidly cornered into a low-volume, small form factor (SFF), low-power segment of the market. On November 7, 2000 (US election day), Transmeta had their initial public offering at the price of $ 21 a share. The value reached a high of $ 50.26 before settling down to $ 46 a share on opening day. This made Transmeta the last of the great high tech IPOs of the dot-com bubble . Their opening day performance would not be surpassed until Google ’s IPO in 2004. The company had its first layoffs in July 2002, reducing

6320-487: Was somewhat better than Intel and AMD offerings, the end user experience (i.e. battery life) only showed a marginal overall improvement. First, the Code Morphing Software (CMS) combined with cache architecture artificially inflated comparisons between benchmarks and real-world applications. This is due to the repetitive nature of benchmarks and their small footprints. The CMS software overhead may have actually been

6400-459: Was working on an “unnamed” Microsoft project. As it turned out, this was a secure platform under the AMD brand for Microsoft's FlexGo program. On October 11, 2006, Transmeta announced that they had filed a lawsuit against Intel Corporation for infringement of ten Transmeta U.S. patents covering computer architecture and power efficiency technologies. The complaint charged that Intel had infringed and

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